Lecture 2: Computer Function

and Interconnection
Acknowledgement: some of the images of the
se slides are captured from the books:
Computer Organization & Architecture and
Operating System Concepts

1
 Objectives
• In this lecturer, the instruction cycle, the major c
omputer system components and the computer
buses are introduced
– The external behaviour of each computer component
– The inter-connection structure and the controls requir
ed to manage the use of the interconnection structure

2
 Instruction Cycle
• Two steps:
– Fetch – read instruction
– Execute – perform the operation

3
 Fetch Cycle
• Program Counter (PC) holds address of next instruction t
o fetch
• Processor fetches instruction from memory location point
ed to by PC
• Increment PC
– Unless told otherwise
– Depends on address size, e.g. for 16 bit bus, PC = PC + 2
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction (decoding) and performs
required actions (execution)

4
 Execute Cycle
• In execute cycle, the CPU performs the operation
which may be:
– Processor-memory
• data transfer between CPU and main memory
– Processor I/O
• Data transfer between CPU and I/O module
– Data processing
• Some arithmetic or logical operation on data
– Control
• Alteration of sequence of operations
• e.g. jump
– Combination of above

5
 Example of Program Execution
Fetch cycle Execute cycle
An addition,
Note that this
example shows
the machine code

6
Instruction Cycle -
State Diagram
Involve I/O operations

CPU internal operations

7
 Interrupts

• Mechanism by which other modules (e.g. I/O) may interrupt normal

sequence of processing
• Program
– e.g. overflow, division by zero
• Timer
– Generated by internal processor timer
– Used in pre-emptive multi-tasking
• I/O
– from I/O controller
• Hardware failure
– e.g. memory parity error

8
Program Flow Control

9
 Interrupt Cycle

• Interrupt cycle is added to instruction cycle

• Processor checks for interrupt
– Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
– Suspend execution of current program
– Save context
– Set PC to start address of interrupt handler routine
– Process interrupt
– Restore context and continue interrupted program

10
Transfer of Control via Interrupts

• In general, Interrupt introduces

programming overhead to the
program but the time required for
handling the overhead is smaller
than the I/O waiting. 11
Instruction Cycle with Interrupts

12
Program Timing: Short I/O Wait

13
Program Timing: Long I/O Wait

14
Instruction Cycle (with Interrupts) -
State Diagram

Interrupt handling

15
 Multiple Interrupts
• At the same time, multiple interrupts may be
required to serve and there are two solutions:
– Disable interrupts (sequential)
• Processor will ignore further interrupts whilst processing one
interrupt
• Interrupts remain pending and are checked after first interrupt
has been processed
• Interrupts handled in sequence as they occur
– Define priorities (nested)
• Low priority interrupts can be interrupted by higher priority
interrupts
• When higher priority interrupt has been processed, processor
returns to previous interrupt

16
Multiple Interrupts - Sequential

17
Multiple Interrupts – Nested

18
Time Sequence of Multiple
Interrupts

Priority: Communication > Disk > Printer

19
 Connecting
• All the units must be connected
• Different type of connection for different type of
unit
– Memory
– Input/Output
– CPU
• The connections among units are mainly through
buses

20
Computer Modules
Consist of N words (address)

Similar to memory

21
 Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
– Read
– Write
– Timing

22
 Input/Output Connection(1)
• Similar to memory from computer’s viewpoint
• Output
– Receive data from computer
– Send data to peripheral
• Input
– Receive data from peripheral
– Send data to computer

23
 Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
– e.g. spin disk
• Receive addresses from computer
– e.g. port number to identify peripheral
• Send interrupt signals (control)

24
 CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives and handle interrupts

25
 Buses
• There are a number of possible interconnection
systems
• Single and multiple BUS structures are most
common
• Bus is a collection of wires
– E.g. 32 bit bus consists of 32 wires
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)

26
 What is a Bus?
• A communication pathway connecting two or
more devices
• Usually broadcast
– One module send a signal and all modules on the bus
can receive
• Often grouped
– A number of channels in one bus
– e.g. 32 bit data bus is 32 separate single bit channels

27
 Data Bus
• Carries data
– Remember that there is no difference between “data”
and “instruction” at this level
• Width is a key determinant of performance
– 8, 16, 32, 64 bit
– Often the wider the bus, the better the performance
but the higher the cost

28
 Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction (data)
from a given location in memory
• Bus width determines maximum memory
capacity of system
– e.g. 8080 has 16 bit address bus giving 64k address
space

29
 Control Bus
• Control and timing information
– Memory read/write signal
– Interrupt request
– Clock signals
• All computer modules require timing signal as all of them are
synchronous devices

30
Bus Interconnection Scheme

31
 Single Bus Problems
• Lots of devices on one bus leads to:
– Propagation delays
• Long data paths mean that co-ordination of bus use can
adversely affect performance
• If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to overcome
these problems
– Special buses are used for specific purpose
• E.g. AGP

32
Traditional (ISA) (with cache)

33
High Performance Bus

34
 Bus Types
• Dedicated
– Separate data & address lines
• Multiplexed or time multiplexing
– Shared lines
– Address valid or data valid control line
– Advantage - fewer lines
– Disadvantages
• More complex control
• Ultimate performance

35
 Bus Arbitration
• Who has the control of the bus?
– More than one module controlling the bus
– e.g. CPU and DMA controller
– Only one module may control bus at one time
– Arbitration may be centralised or distributed

36
 Centralised Arbitration
• Single hardware device controlling bus access
– Bus Controller
– Arbiter
• May be part of CPU or separate

37
 Distributed Arbitration
• No central controller
• Each module may claim the bus
• Control logic on all modules

38
 Timing
• Co-ordination of events on bus
• Synchronous
– Events determined by clock signals
– Control Bus includes clock line
– A single 1-0 is a bus cycle
• The fastest signal in a computer system
– All devices can read clock line
– Usually sync on leading edge
– Usually a single cycle for an event

39
Synchronous Timing Diagram

40
Asynchronous Timing – Read
Diagram 1. CPU prepares
control signals
and address
2. CPU issues the
read command
3. Memory module
responds the
request by placing
the data on the
bus
4. CPU
acknowledges
that the data is
read
5. Read command is
end and the
acknowledge
signal is end also

1 2 3 4 5
The signals are issued depending on the previous signals
41
Asynchronous Timing – Write
Diagram

42
The writing operation is left for your exercise
 Summary
• In this lecture, the internal structure of a
computer is introduced
– CPU architecture
– Program flow
– Interrupt
– Buses
• In next lecture, CPU Function and structure are
studied

END
43