MEMORY

MANAGEMENT

CHAPTER IV
 CONTENT
Memory Management Background, Swapping, Contiguous
Memory Allocation Schemes, Paging, Segmentation,
Virtual Memory Management: Background, Demand
paging scheme, Process Creation, Page Replacement
Policies, Allocation of Frames, Thrashing
BACKGROUND
• Computer solves the problem
• CPU executes the instruction.
• Instructions are stored into Memory.
• Memory Hierarchy – Size ? Speed ? Access ?
BACKGROUND
• Programs are stored into secondary memory
• CPU cannot access Secondary memory directly.
• Programs are loaded into main memory and then CPU fetched it directly.
• Number of processes loaded into main memory is Degree of
multiprogramming.
BACKGROUND- ADDRESS BINDING
• Address binding of instructions and data to memory addresses can happen at
three different stages.
Compile time: If memory location known a priori, absolute code can be
generated; must recompile code if starting location changes.
Load time: Compiler must generate re-locatable code if memory location is not
known at compile time. In this case, Final binding is delayed.
Execution time: Binding delayed until run time if the process can be moved
during its execution from one memory segment to another.

Program

CPU Main Memory Secondary Memory

MULTISTEP PROCESSING OF A USER PROGRAM
LOGICAL VS. PHYSICAL ADDRESS
– Logical address – generated by the CPU; also referred to as virtual address.
– Physical address – address seen by the memory unit.
• At compile and load time, LA & PA both are same.
• At run time, they are not similar.
• Hardware device that maps virtual to physical address.
In MMU scheme, the value in the relocation register is added to every address
generated by a user process at the time it is sent to memory.
• The user program deals with logical addresses; it never sees the real physical
addresses.
DYNAMIC RELOCATION USING A RELOCATION REGISTER

8
LINKING
Static Linking:
• All objects module are copied in one executable file. All library function file
are also copied in one executable code.
• Load time larger, If bug then need to recompile everything.

Dynamic Linking
• Linking postponed until execution time.
• Small piece of code, stub, used to locate the appropriate memory-resident
library routine.
• Stub replaces itself with the address of the routine, and executes the routine.
• Dynamic linking is particularly useful for libraries.

9
LOADING
• Load programs (2ry memory) to main memory.
• Static Loading: Load all programs into main memory.

Dynamic Loading
• Routine is not loaded until it is called
• Better memory-space utilization; unused routine is never loaded.
• Useful when large amounts of code are needed to handle infrequently
occurring cases.
• No special support from the operating system is required implemented
through program design.
10
 SWAPPING
• A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution.

• Backing store – fast disk large enough to accommodate copies of all

memory images for all users; must provide direct access to these
memory images.

• Roll out, roll in – swapping variant used for priority-based scheduling

algorithms; lower-priority process is swapped out so higher-priority
process can be loaded and executed.
SCHEMATIC VIEW OF SWAPPING
MEMORY MANAGEMENT TECHNIQUES

OS

Memory
 FIXED PARTITION
• Number of partitions are
fixed.
OS OS
• Size of each partition may or
may not be same.
4 MB 4 MB • Spanning is not allowed.
8 MB 4 MB • Internal Fragmentation.
8 MB 4 MB • There is limit in process size.
4 MB 4 MB
• Limitation on degree of
multiprogramming.
• External Fragmentation.
VARIABLE PARTITION
• Number of partitions are not fixed.
OS
• Spanning is not allowed.
• No restriction on degree of Multiprogramming
• No Internal Fragmentation.
• No limitation on process size.
• External Fragmentation.
• Solution to External Fragmentation :
Compaction
ALGORITHMS: FIRST FIT, BEST FIT, WORST FIT
• First-fit: Allocate the first hole that is big enough. Searching can
start at the beginning of the set of holes or where previous first fit
search ended.
• Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size. Produces the smallest leftover
hole.
• Worst-fit: Allocate the largest hole; must also search entire list.
Produces the largest leftover hole.
 FIRST FIT
• Allocate the first hole that is big enough.
Searching can start at the beginning of
the set of holes or where previous first fit
search ended.
• If process P1 comes and its size is 15.
• Simple, Fast and Convenient
BEST FIT
• Allocate the smallest hole
that is big enough; must
search entire list, unless
ordered by size. Produces
the smallest leftover hole.
• If process P1 comes and its
size is 15.
• Small internal
fragmentation but this can
be disadvantage.
WORST FIT
• Allocate the largest hole;
must also search entire list.
Produces the largest
leftover hole.
• If process P1 comes and its
size is 15.
• Large Internal
Fragmentation but this can
be advantage
NUMERICAL BASED ON ALGORITHM
• Given memory partition of 500 KB, 200 KB, 300 KB and 600 KB (in order),
how would each of the first fit, best fit and worst fit algorithms place processes
of 212 KB, 417 KB, 112 KB and 426 KB (in order)

500 KB

200 KB

300 KB

600 KB
 • Given memory partition of 500 KB, 200 KB, 300 KB
FIRST FIT and 600 KB (in order), how would first fit algorithm
place processes of 212 KB, 417 KB, 112 KB and 426
KB (in order)

• P1= 212 KB, P2=417 KB, P3=112 KB, P4= 426 KB

500 KB P1

Internal Fragmentation = 559

200 KB P3

300 KB Is there a external fragmentation = Yes

600 KB P2
P4 is in waiting
 • Given memory partition of 500 KB, 200 KB, 300
BEST FIT KB and 600 KB (in order), how would best fit
algorithm place processes of 212 KB, 417 KB, 112
KB and 426 KB (in order)

• P1= 212 KB, P2=417 KB, P3=112 KB, P4= 426

500 KB P2 KB

200 KB P3
Internal Fragmentation = (500-417)+(200-
300 KB P1 112)+(300-212)+(600-426)= 433

600 KB P4
Is there a external fragmentation = No
 • Given memory partition of 500 KB, 200 KB, 300 KB
WORST FIT and 600 KB (in order), how would worst fit algorithm
place processes of 212 KB, 417 KB, 112 KB and 426
KB (in order)

• P1= 212 KB, P2=417 KB, P3=112 KB, P4= 426 KB

500 KB P2
Internal Fragmentation = (500-417)+(300-112)+(600-
200 KB 212)= 659

300 KB P3
Is there a external fragmentation = YES

600 KB P1
P4 is in wait.
FRAGMENTATION (SUMMARIZED…)

• External Fragmentation – total memory space exists to satisfy a

request, but it is not contiguous.
• Internal Fragmentation – allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a
partition, but not being used.
• Reduce external fragmentation by compaction
– Shuffle memory contents to place all free memory together in one large block.
– Compaction is possible only if relocation is dynamic, and is done at execution
time.
– If address are relocated dynamically, relocation requires only moving the
program and data and then changing the base register
PAGING
• Logical address space of a process can be noncontiguous; process is allocated
physical memory whenever the latter is available.
• Divide main memory into fixed-sized blocks called frames
• Divide logical memory (process) into blocks of same size called pages.
• Keep track of all free frames.
• To run a program of size n pages, need to find n free frames and load program.
• Set up a page table to translate logical to physical addresses.
• Internal fragmentation.

Operating System Concepts

PAGING MODEL

Operating System Concepts

ADDRESS TRANSLATION ARCHITECTURE
– PAGING HARDWARE

Operating System Concepts

 PAGING EXAMPLE- 32 BYTE MEMORY WITH 4 BYTE PAGE

PA= (frame no. *

page size)+ offset

Operating System Concepts

IMPLEMENTATION OF PAGE TABLE
• Page table is kept in main memory.
• Page-table base register (PTBR) points to the page table.
• Page-table length register (PRLR) indicates size of the page table.
• In this scheme every data/instruction access requires two memory
accesses. One for the page table and one for the data/instruction.
• The two memory access problem can be solved by the use of a
special fast-lookup hardware cache called associative memory or
translation look-aside buffers (TLBs)

Operating System Concepts

ASSOCIATIVE MEMORY
• The TLB is associative, high speed memory.
• Associative memory – parallel search
Page # Frame #

Hardware is expensive, entries are between 64 to 1024

If page no is not in TLB called TLB miss,
memory reference to the page table must be made.
Some TLB allow entries to be wired down(Kernel code)
Some TLB store Address space identifier(ASIDs) in each TLB entry

Operating System Concepts

PAGING HARDWARE WITH TLB

Operating System Concepts

MEMORY PROTECTION
• Memory protection implemented by associating protection bit with
each frame.

• Valid-invalid bit attached to each entry in the page table:

– “valid” indicates that the associated page is in the process’ logical address
space, and is thus a legal page.
– “invalid” indicates that the page is not in the process’ logical address space.

Operating System Concepts

VALID (V) OR INVALID (I) BIT IN A PAGE TABLE

Operating System Concepts

SHARED PAGES
• Shared code
– An advantage of paging is sharing common code which is particularly important in time
sharing system.
– One copy of read-only (reentrant) code shared among processes (i.e., text editors,
compilers, window systems).
– Shared code must appear in same location in the logical address space of all processes.

• Private code and data

– Each process keeps a separate copy of the code and data.
– The pages for the private code and data can appear anywhere in the logical address space.

Operating System Concepts

SHARED PAGES EXAMPLE

Operating System Concepts

PAGE TABLE STRUCTURE
• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables

Operating Systems 6KS01 36

HIERARCHICAL PAGE TABLES

• Break up the logical address space into multiple page tables.

• A simple technique is a two-level page table.

Operating Systems 6KS01 37

 TWO-LEVEL PAGING EXAMPLE
• A logical address (on 32-bit machine with 4K page size) is divided into:
– a page number consisting of 20 bits.
– a page offset consisting of 12 bits.
• Since the page table is paged, the page number is further divided into:
– a 10-bit page number.
– a 10-bit page offset.
• Thus, a logical address is as follows:

page number page offset

pi p2 d

10 10 12
where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table.

Operating Systems 6KS01 38

TWO-LEVEL PAGE-TABLE SCHEME

Operating Systems 6KS01 39

ADDRESS-TRANSLATION SCHEME
• Address-translation scheme for a two-level 32-bit paging architecture

Operating Systems 6KS01 40

HASHED PAGE TABLES
• Common in address spaces > 32 bits.

• The virtual page number is hashed into a page table. This page table
contains a chain of elements hashing to the same location.

• Virtual page numbers are compared in this chain searching for a

match. If a match is found, the corresponding physical frame is
extracted.

Operating Systems 6KS01 41

HASHED PAGE TABLE

Each element consists of three fields (i) virtual Page No , (ii) Value of the
mapped page frame (iii) a pointer to the next element in the linked list
Operating Systems 6KS01 42
INVERTED PAGE TABLE
• Entry consists of the virtual address of the page stored in that real
memory location, with information about the process that owns that
page.
• Decreases memory needed to store each page table, but increases
time needed to search the table when a page reference occurs.
• Use hash table to limit the search to one — or at most a few —
page-table entries.

Operating Systems 6KS01 43

INVERTED PAGE TABLE ARCHITECTURE

Operating Systems 6KS01 44

SEGMENTATION
• Memory-management scheme that supports user view of memory.
• A program is a collection of segments. A segment is a logical unit such as:
main program,
procedure,
function,
method,
object,
local variables, global variables,
common block,
stack,
symbol table, arrays

Operating System Concepts

USER’S VIEW OF A PROGRAM

Operating System Concepts

LOGICAL VIEW OF SEGMENTATION
1

4
1

3 2
4

user space physical memory space

Operating System Concepts

SEGMENTATION ARCHITECTURE
• Logical address consists of a two tuple:
<segment-number, offset>,
• Segment table – maps two-dimensional physical addresses; each
table entry has:
– base – contains the starting physical address where the segments reside in
memory.
– limit – specifies the length of the segment.

Operating System Concepts

SEGMENTATION HARDWARE

Operating System Concepts

EXAMPLE OF SEGMENTATION

Operating System Concepts

NUMERICAL
Consider given segment table and find out physical address for following logical address
a) 0, 430 b) 1, 10 c) 2,500 d) 3,400 e) 4,112

Segment Base Length

0 219 600
1 2300 14
2 90 100
3 1327 580
4 1952 96