GXEST203- Foundations of

computing: From hardware essential

to web design

S2 CSE
NUMBER SYSTEMS

 A number system is a writing system for expressing numbers;

 it is a mathematical notation for representing numbers in a consistent manner using symbols or
digits.
 Different number systems are used in various fields of computing, mathematics, and everyday
life.
 The main types of number systems are:
1. Decimal Number System (Base 10)
2. Binary Number System (Base 2)
3. Octal Number System (Base 8)
4. Hexadecimal Number System (Base 16)
Decimal Number System

 The decimal system is the most commonly used number system in everyday life and is
based on 10 digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
 Each place value in a decimal number is a power of 10.
 For example, in the number 235:
• 2×10^2=200
• 3×10^1=30
• 5×10^0=5 Total: 200+30+5=235
 The decimal system is positional, meaning the value of each digit depends on its position
in the number.
Binary Number System

 The binary system is used internally by almost all modern computers and computer-based devices
because it is straightforward to implement with digital electronic circuitry.
 It uses only two digits: 0 and 1.
 These two symbols represent two states: 0 for off, and 1 for on.
 Binary numbers are written using powers of 2. For example, the binary number 1011 represents:
• 1x2^3-8
• 0x2^2-0
• 1×2^1-2
• 1×2^0-1
• Total: 8+0+2+1=11in decimal.
Octal Number System

 The octal system is a base-8 number system that uses digits from 0 to 7.
 Each digit represents a power of 8.
 It is sometimes used in computing as a shorthand for binary numbers because every octal
digit corresponds to exactly three binary digits.
 For example, the octal number 157 represents:
 1×8^2=64
 5x8^1=40
 7x8^0=7
 Total: 64+40+7=111 in decimal.
Hexadecimal Number System

 The hexadecimal system is a base-16 number system that uses 16 symbols: the digits 0 to 9 and
the letters A to F (or a to f) to represent values from 10 to 15.
 Hexadecimal is often used in computing and digital electronics as a more compact representation
of binary numbers.
 One hexadecimal digit corresponds to 4 binary digits (bits).
 For example, the hexadecimal number 1F3 represents:
o 1×16^2=256
o F(15)×16^1=240
o 3×16^0=3
o Total: 256+240+3=499 in decimal.
DATA STORAGE UNITS

 Data storage units are standardized measurements used to quantify digital information.
 Storage capacity is typically measured using various units, each representing different
scales of data.
 The most common units used to measure digital storage are:
1. Bits
 Bits are the basic building blocks of not only data storage, but all computers.
 Computers work in binary digits, combining 0's and 1's in countless patterns.
 These binary digits are known as bits, and are the smallest possible unit for data storage.
2. Byte
 A byte consists of 8 bits and is the standard unit of storage used to measure file sizes and
memory capacity in most systems.
 For one character of text typically takes up one byte.
 All example, memory storage is expressed in terms of bytes, so although bits might be
the foundation upon which data storage is built, bytes are the building blocks that truly
denote the usability of any one storage solution.
3. Kilobyte (KB)
 1 KB = 1,024 bytes (in binary systems). In decimal (SI system), 1 KB is often considered
1,000 bytes. Kilobytes are used to measure small files such as text documents.
4. Megabyte (MB)
 1 MB = 1,024 KB = 1,048,576 bytes (binary). In the SI decimal system, 1 MB =
1,000,000 bytes. Megabytes are used to measure the size of larger files like images, audio
files, and software applications.
4. Gigabyte (GB)
 1 GB = 1,024 MB = 1,073,741,824 bytes (binary).
 In the decimal system, 1 GB = 1,000,000,000 bytes. Gigabytes are commonly used to
measure the storage capacity of devices like smartphones, SSDs, and hard drives.
Data Storage Units
BINARY REPRESENTATION OF DATA
AND NUMBERS

 Binary Representation of Data and Numbers is the use of the binary number system (base-
2) to represent data in computing.
 In binary, only two digits are used: 0 and 1. This is because computers use electrical
signals that can be in one of two states, typically represented as off (0) and on (1).
 The base-2 system is the positional notation with 2 as a radix.
 The binary system is applied internally by almost all latest computers and computer-based
devices because of its direct implementation in electronic circuits using logic gates. Every
digit is referred to as a bit.
Converting Decimal to Binary

 To convert a decimal number to binary, we can repeatedly divide the number by 2 and
record the remainders.
 To convert 13 to binary
1. Divide 13 by 2. The quotient is 6, and the remainder is 1.
2. Divide 6 by 2. The quotient is 3, and the remainder is 0.
3. Divide 3 by 2. The quotient is 1, and the remainder is 1.
4. Divide 1 by 2. The quotient is 0, and the remainder is 1.
5. Now, take the remainders from bottom to top: 1101.
 2. To convert 47 to binary
1. Divide 47 by 2. The quotient is 23, and the remainder is 1.
2. Divide 23 by 2. The quotient is 11, and the remainder is 1.
3. Divide 11 by 2. The quotient is 5, and the remainder is 1.
4. Divide 5 by 2. The quotient is 2, and the remainder is 1.
5. Divide 2 by 2. The quotient is 1, and the remainder is 0.
6. Divide 1 by 2. The quotient is 0, and the remainder is 1.
7. Now, take the remainders from bottom to top: 101111.
 To convert 0.54 to binary
Convert 10110 to binary
Convert 0.1101 to decimal
Integer Representation

 Integer representation in computers refers to how whole numbers

(both positive and negative) are stored and manipulated in binary
form.
 There are different ways to represent integers, depending on
whether we are dealing with signed or unsigned integers, and the
size of the number (e.g., 8-bit, 16-bit, 32-bit, 64-bit).
Unsigned Integer Representation

 An unsigned integer can only represent non-negative whole numbers (0 or positive numbers).
 It uses all its bits to represent the magnitude of the number.
 For example: 8-bit unsigned integer can represent numbers from 0 to 255 (since 2^8 = 256 possible
values)
 10101010 (binary)- 1x27+0x26+ 1x25+0x24+1x23+0x22+1×21 +0×20-128 +32 +8 +2 = 170 (decimal)
 Thus, 10101010 in binary= 170 in decimal
Signed Integer Representation

 A signed integer can represent both positive and negative whole numbers.
 There are a few different methods for encoding signed integers in binary.
1. Sign and Magnitude Representation:
 In sign and magnitude representation, the most significant bit (MSB) is used to represent
the sign of the number: 0 indicates a positive number and 1 indicates a negative number.
 The remaining bits represent the magnitude(absolute value) of the number.
 For example, using 8 bits:+5 is represented as: 00000101 (binary) and
-5 is represented as: 10000101 (binary) (MSB = 1 indicates the negative sign)

• The limitation of sign and magnitude is that there are two representations for zero: +0 (00000000) and -
0 (10000000), which is inefficient.
2. Two's Complement Representation
 In two's complement representation, negative numbers are represented by inverting the bits of the
number's absolute value and then adding 1 to the result.
 This method is widely used because it simplifies arithmetic operations and avoids having two
representations for zero.
 For example, using 8 bits:+5 is represented as: 00000101 (binary) and-5 is represented as:Invert
00000101 → 11111010Add 1-11111011 (binary)
 Two's complement works because of the way it handles overflow and it allows for simpler hardware
implementation of addition and subtraction.
 For example, to convert a positive number to its negative counter part in two's
complement:
1. Write the number in binary.
2. Invert all the bits.
3. Add 1 to the result.
 Convert +5 to binary (8-bit): +5=00000101.
 Now, to convert -5:
• 1. Invert 00000101 → 11111010
• 2. Add 1-11111011 (binary)Thus, -5 is represented as 11111011 in two's complement.
Binary Arithmetic
Binary Addition

 In binary arithmetic, the process of adding two binary numbers is called binary addition.
 Binary numbers consist of only 0 and 1. In the binary addition, a carry is generated when
the sum is greater than 1.
 Rules:
Example
Binary Subtraction

 Binary subtraction is a mathematical operation used to find the difference between two binary
numbers.
 In binary subtraction, each bit of the binary numbers is subtracted, starting from the rightmost
bit.
 The Borrowing process happens when subtracting 1 from 0.
 Rules:
0–0=0
1–0=1
1–1=0
0 – 1 (requires borrowing, becomes 10 – 1=1)
Example

 1. Subtract 1101 from 10110

10110
- 1101
-----------------------
1001
2. Subtract 101 from 1111

3. Subtract 1010 from 1101

Binary Multiplication

 Binary multiplication is the process of multiplying two binary numbers and obtain their
product.
 In binary multiplication, we multiply each bit of one binary number by each bit of another
binary number and then add the partial products to obtain the final product.
 Rules:
0x0=0
1x0=0
0x0=0
1x1=1
Example

 Multiply 1101 by 11.

Binary Division

 Binary division is one of the basic arithmetic operations used to find the quotient and
remainder when dividing one binary number by another.
 Example :
Divide 110011 by 11.
Procedure

• Start dividing from the leftmost bits of the dividend by the divisor.
• Multiply the quotient obtained by the divisor and subtract from the dividend.
• Bring down the next bits of the dividend and repeat the division process until all the bits
of given divided are used.
9’s Complement

 The 9's complement of a number is found by subtracting each digit in the number from 9. It is commonly
used in subtraction operations in digital electronics and computer systems.
Steps to Find 9's Complement:
1. Write the given number.
2. Subtract each digit of the number from 9.
Example:
Let's calculate the 9's complement of the number 4567.
1. Write the number:
4567
2. Subtract each digit from 9:
o9-4=5
o9-5=4
o9-6=3
o9-7=2
3. Resulting 9's complement: 5432
Steps for Subtraction Using 9's
Complement:

 To compute A−B using 9's complement:

1. Find the 9's complement of B: Subtract each digit of B from 9.
2. Add A and the 9's complement of B: Perform regular addition.
3. Adjust the result:
o If there's a carry, add 1 to the result and discard the carry.
o If there's no carry, take the 9's complement of the result to get the negative value.
Example: 4567−1234

Step 1: Find the 9's complement of B (1234):

● 9−1=8
● 9−2=7
● 9−3=6
● 9−4=5
The 9's complement of 1234is 8765.
Step 2: Add A (4567) and 9's complement of B (8765):
4567+8765=13332
Step 3: Adjust the result:
● Since there is a carry (1), add it to the least significant digit:3332+1=3333
Thus, the result of 4567−1234 is 3333.
ASCII Vs Unicode
Instruction Cycle

 The CPU uses a cycle known as the Instruction cycle to process all of these instructions
and operations.
 The instruction cycle is the time it takes a CPU to execute and retrieve a complete
instruction . While this cycle can vary from CPU to CPU, they typically consist of the
following stages:
1. Fetch: When we power on our computers, the CPU is ready to process instructions. As
instructions are received, a register in the CPU known as the Program Counter (PC) holds the
memory address of the next instruction to be processed. When it comes time to begin
processing the instruction, the CPU copies the memory location and stores the duplicated data
in another register on the CPU known as the Instruction Register (IR). Decoding occurs once
the instruction's memory is available.
 2. Decode: The next step in the cycle is to decode the instruction. During this stage, the
Control Unit determines what the instruction recorded in the IR implies.
 3. Execute: In this phase, the instruction is carried out!
 4. Memory Access: The memory access step retrieves any data required to perform an
instruction. This stage is only activated if the instruction demands data from memory.
 5. Registry Write-Back: If the execution of the instruction has any effect on data, the
registry write-back step is used. This is another stage that may or may not occur during
the cycle.
key components

 Program Counter (PC): Keeps track of the address of the next instruction.
 Memory Address Register (MAR): Holds the address of the instruction or data to be
accessed.
 Memory Buffer Register (MBR): Holds the instruction or data that has been fetched from
or will be written to memory.
 Instruction Register (IR): Holds the currently decoded instruction.
 Control Unit (CU): Decodes the instruction and generates the necessary control signals.
 Arithmetic Logic Unit (ALU): Performs mathematical and logical operations.
Advantages

1. Standardization: The instruction cycle provides a standard way for CPUs to execute
instructions, which allows software developers to write programs that can run on multiple
CPU architectures.
2. Efficiency: By breaking down the instruction execution into multiple steps, the CPU can
execute instructions more efficiently.
3. Pipelining: The instruction cycle can be pipelined, which means that multiple instructions
can be in different stages of execution at the same time. This improves the overall
performance of the CPU, as it can process multiple instructions simultaneously.
Disadvantages

 1. Overhead: The instruction cycle adds overhead to the execution of instructions, as each
instruction must through multiple stages before it can be executed. This overhead can
reduce the overall performance of the CPU.
 2. Complexity: The instruction cycle can be complex to implement, especially if the CPU
architecture and instruction set are complex. This complexity can make it difficult to
design, implement, and debug the CPU.
 3. Limited parallelism: While pipelining can improve the performance of the CPU, it also
has limitations. For example, some instructions may depend on the results of previous
instructions, which limits the amount of parallelism that can be achieved.
Fetch – Execute Instruction Cycle

 It is the basic operation cycle of a computer (also known as the fetch decode execute
cycle).
 During the fetch execute cycle the computer retrieves a program instruction from its
memory. It then establishes and carries out the actions that are required for that
instruction.
 The cycle of fetching, decoding, and executing an instruction is continually repeated by
the CPU whilst the computer is turned on.
1. Fetch Stage:

 During the fetch phase, the CPU retrieves an instruction from memory (RAM) to execute.
Step 1: Program Counter (PC) provides the address of the next instruction.
Step 2: The instruction is fetched from memory.
CPU uses the memory address in the PC to access the instruction memory. The memory
address is loaded into the Memory Address Register (MAR). Then, the instruction is fetched
from the memory and placed into the Memory Buffer Register.
Step 3: Increment the Program Counter.
Step 4: The instruction is loaded into the Instruction R(IR)
2.Execute Stage

During the execute phase, the CPU performs the action specified by the instruction.
Step 5: Decode the instruction: The Control Unit (CU) decodes the instruction stored in the
Instruction Register (IR) to determine the operation to perform.
Step 6: Operate on data (if needed): If the instruction involves an operation, such as an
arithmetic or logical operation, the Arithmetic Logic Unit (ALU) performs the operation.
Step 7: Write back results (if necessary): If the instruction produces a result (for example, a
calculation), the result is written back into a register or memory location.
3. Repeat the cycle

 Once the instruction has been executed, the CPU returns to the fetch phase and retrieves
the next instruction using the updated Program Counter (PC).
 This cycle repeats until the program completes or a halt condition is encountered.
 Simple assembly language instruction:
MOV RI, R2
This instruction copies the contents of register R2 into register R1.
In the Fetch phase, the CPU retrieves the instruction from memory.
Step 1: The Program Counter (PC) holds the address of the next instruction to be fetched.
Assume the address of the MOV R1, R2instruction is 0x2000.
Step 2: The address 0x2000 is copied to the Memory Address Register (MAR). The instruction
stored at address 0x2000 (which is MOV R1, R2) is fetched from memory and placed into the
Memory Buffer Register (MBR).
Step 3: After fetching the instruction, the Program Counter (PC) is incremented to point to the
next instruction (for example, to address 0x2004).
Step 4: The instruction in the MBR is transferred to the Instruction Register (IR). The IR now
holds MOV R1, R2.
 In the Decode phase, the CPU decodes the instruction to determine what action needs to
be taken.
 Step 5: The Control Unit (CU) examines the instruction in the IR. It determines that the
instruction is a Move (MOV) operation, which means the contents of register R2 need to
be copied into register R1.
 Step 6: The Control Unit (CU) sends signals to:
 Read the data from register R2.
 Write the data into register R1.
 In the Execute phase, the CPU performs the operation specified by the instruction.
 Step 7: Since this is a Move instruction, the CPU doesnot need to perform a calculation.
It simply copies the data from R2 to R1.
 Step 8: The contents of R2 are written into R2.
 Step 9:The Program Counter (PC) is already updated during the fetch stage, CPU is ready
to fetch the next instruction from memory.
. Complete Instruction Cycle
(Fetch-Decode-Execute-Store)

 The complete cycle follows this sequence:

1. Fetch the instruction from memory.
2. Decode the instruction to understand its operation.
3. Execute the operation using ALU or registers.
4. Store the result (if needed) back to memory
 Example of an Instruction Cycle

 Instruction: ADD A, B (Add contents of B to A)

1. Fetch: CPU fetches ADD A, B from memory.
2. Decode: Control Unit identifies it as an addition operation.
3. Execute: ALU adds values of A and B.
4. Store: Result is stored in A.
CPU Architecture

 Central Processing Unit (CPU) is the brain of a computer, responsible for executing instructions and
performing calculations. It follows a structured architecture that allows it to process data efficiently.
 Major Components of a CPU
1. Arithmetic Logic Unit (ALU):
o Performs arithmetic (addition, subtraction, multiplication, division) and logical (AND, OR, NOT, XOR) operations.
2. Control Unit (CU):
o Directs operations by fetching, decoding, and executing instructions.
o Manages the flow of data between the CPU, memory, and input/output devices.
3. Registers:
o Small, high-speed storage units inside the CPU for temporary data storage.
o Examples of registers:
 Program Counter (PC): Holds the address of the next instruction.
 Instruction Register (IR): Stores the current instruction.
 Accumulator (ACC): Temporarily holds intermediate results.
4. Memory (RAM) :
O CPU interacts with memory (RAM) to fetch instructions and store intermediate data during processing.
Functions:
 Stores instructions and data that the CPU needs for execution.
 Provides fast access to data that the CPU can retrieve and manipulate.
5. Bus System:
O It is used for communication between the CPU and other parts of the computer such as memory and input/output
devices..
o Types:
▪ Data Bus: Transfers actual data.
▪ Address Bus: Transfers memory addresses.
▪ Control Bus: Sends control signals.
CPU Instruction Cycle (Fetch-Decode-
Execute Cycle)

 The CPU processes instructions in a repeated cycle known as the

Fetch-Decode-Execute
cycle:
1. Fetch: The control unit retrieves an instruction from memory (RAM) and stores it in the
Instruction Register (IR).
2. Decode: The instruction is analyzed to determine the required operation and operands.
3. Execute: The ALU or other components perform the operation.
4. Store: The result is written back to a register or memory.
Arithmetic Logic Unit (ALU)

 The Arithmetic Logic Unit (ALU) is a key component of the CPU responsible for
performing
all arithmetic and logical operations. It operates as the computational core of the
processor.
 Functions of ALU
The ALU is responsible for:
1. Arithmetic Operations: Addition, subtraction, multiplication, and division.
2. Logical Operations: AND, OR, NOT, XOR, NAND, NOR, XNOR.
3. Bitwise Operations: Bit shifting (left shift, right shift) and bit manipulation.
4. Comparison Operations: Checking if values are equal, greater than, or less than.
5. Increment/Decrement Operations: Increasing or decreasing values by one.
Components of ALU

 The ALU consists of various subcomponents that work together to perform computations:
(i) Operand Registers
● Temporarily store the input values for an operation.
● Examples: Accumulator (ACC), General Purpose Registers (R1, R2, etc.)
(ii) Arithmetic Unit
● Performs mathematical calculations like addition, subtraction, multiplication, and division using circuits like adders and
multipliers.
(iii) Logic Unit
● Executes logical operations such as AND, OR, XOR, and NOT using logic gates.
(iv) Status Flags
● Stores information about the result of an operation.
● Example flags:
o Zero (Z) Flag: Set if the result is zero.
o Carry (C) Flag: Set if there is a carry from an addition operation.
o Sign (S) Flag: Set if the result is negative.
Working of ALU

 The ALU follows a systematic process for executing instructions:

Step 1: Input Fetching
● The Control Unit (CU) fetches the instruction from memory and sends required data to the ALU.
Step 2: Operation Execution
● The ALU performs the required arithmetic or logical operation on the input values.
Step 3: Result Storage
● The computed result is stored in the Accumulator (ACC) or a register.
● If necessary, the result is sent back to memory.
Step 4: Flag Update
● The status flags (Zero, Carry, Sign, Overflow) are updated based on the result.
Role of ALU in CPU Performance

 The speed of ALU operations directly affects CPU performance

since most computing tasks involve arithmetic and logic calculations.
 Modern CPUs may have multiple ALUs to perform operations in
parallel, increasing processing efficiency.
 ALUs are designed using combinational logic circuits such as full
adders, multiplexers,
and logic gates.
Registers in CPU

 Registers are small, high-speed storage units located inside the CPU, used to
store temporary
data, instructions, and addresses.
 Characteristics of Registers:
● Faster than cache and main memory.
● Store data temporarily for quick processing.
● Used in the fetch-decode-execute cycle for efficient execution.
Types of Registers:
1. General-Purpose Registers (GPRs)
o Used for general data storage during execution.
o Example: AX, BX, CX, DX (in x86 architecture).
2. Special-Purpose Registers
o Designed for specific tasks, such as holding memory addresses, flags, or counters.
Special-Purpose Registers in a CPU:

Register Function
Program Counter (PC) Holds the address of the next instruction to be
executed.
Instruction Register (IR) Stores the current instruction being executed.
Memory Address Register Holds the address of the memory location being
(MAR) accessed.
Memory Data Register Temporarily stores data read from or written to
(MDR) memory.
Accumulator (ACC) Holds intermediate arithmetic and logical results.
Stack Pointer (SP) Points to the top of the stack in memory.

Status/Flag Register Stores flags indicating CPU status (e.g., Zero

 Importance of Registers in CPU Operations:
● Enable fast data retrieval and processing.
● Reduce dependence on slower memory (RAM).
● Facilitate efficient execution of instructions.
Control Unit (CU)

 The Control Unit (CU) is a critical component of the CPU that directs the
execution of instructions by coordinating data flow between the CPU,
memory, and input/output devices.
 Functions of the Control Unit:
1. Instruction Fetching – Retrieves instructions from memory.
2. Instruction Decoding – Interprets the instructions to determine required operations.
3. Generating Control Signals – Directs other CPU components, such as the ALU and
registers.
4. Managing Data Flow – Ensures proper movement of data between registers, memory,
and I/O devices.
Types of Control Units:

 Hardwired Control Unit:

o Uses fixed logic circuits to generate control signals.
o Faster but less flexible.
o Used in RISC (Reduced Instruction Set Computing) processors.
2. Microprogrammed Control Unit:
o Uses a control memory to store microinstructions.
o More flexible but slightly slower.
o Used in CISC (Complex Instruction Set Computing) processors.
Role of Registers and Control Unit in the
Instruction Cycle

 The Fetch-Decode-Execute Cycle is controlled by the CU and assisted by registers:

1. Fetch Phase:
o The Program Counter (PC) sends the address of the next instruction to the
Memory Address Register (MAR).
o The instruction is retrieved from memory and placed in the Instruction Register (IR).
2. Decode Phase:
o The Control Unit (CU) interprets the instruction in the IR and prepares control
signals.
3. Execute Phase:
o The ALU processes the instruction using data from registers.
o The Control Unit sends signals to store results in appropriate locations.
4. Store Phase:
Common CPU Architectures:
Complex Instruction Set Computer (CISC)
Architecture

 CISC (Complex Instruction Set Computing) is a type of microprocessor architecture that aims to
reduce the number of instructions per program, at the cost of using more complex instructions.
 Single instruction can execute multiple low- level operations (such as loading from memory,
performing an arithmetic operation, and storing the result back to memory) in a single
instruction cycle.
 Reduce the number of instructions required to perform a task, thus potentially improving
performance for certain applications.
key characteristics of CISC architecture

1.Complex Instructions: CISC processors have a large number of instructions, many of which can
perform operations in a single instruction (e.g., load from memory, complex perform arithmetic, and store
back in one instruction).
2. Variable-Length Instructions: CISC instructions can vary in length, depending on the operation and
operands involved.
3. Fewer Instructions: Since CISC allows for complex operations in a single instruction, fewer
instructions may be required to complete a task compared to other architectures like RISC.
4. Memory-to-Memory Operations: CISC processors can perform operations directly on memory
without needing to load data into registers first.
5. Backward Compatibility: CISC architectures, especially in the case of x86 processors, often maintain
backward compatibility with older programs, allowing software written for older processors to run on
newer ones.
Advantages of CISC:
 Reduced Instruction Count: Complex instructions mean that fewer instructions
are needed for a given task, potentially reducing the overall program size.
 Improved Performance for Specific Tasks: For certain applications that
require complex operations (like mathematical calculations or string processing),
CISC can outperform simpler architectures.
Disadvantages of CISC:
 Slower Clock Speeds: The complexity of each instruction may lead to slower
execution compared to simpler instructions.
 Complex Decoding: The need to decode variable-length instructions adds
complexity to the processor design.
Reduced Instruction Set Computing (RISC)
Architecture

 The primary goal of RISC is to simplify the design and operation of processors by limiting the
number of instructions and making each instruction execute in a single clock cycle (or a minimal
number of cycles).
 RISC architectures are designed to increase performance through simplicity, efficiency, and
parallelism.
 Key Characteristics of RISC Architecture

1. Simplified Instructions: RISC processors use a small set of instructions, each designed to execute in a single cycle (or as few cycles as
possible). These instructions tend to be simple and perform a single, well-defined task.
2. Fixed-Length Instructions: Unlike CISC, where instruction lengths can vary, RISC instructions are typically of fixed length (e.g., 32
bits), making instruction decoding faster and simpler.
3.Load/Store Architecture: RISC processors separate memory access and arithmetic operations. Memory can only be accessed through
specific load and store instructions, and all other operations are performed on registers.
4. Registers as the Primary Data Storage: RISC processors use a large number of general-purpose registers.
5. Fewer Addressing Modes: RISC architectures typically have simpler, fewer addressing modes compared to CISC, which makes the
processor easier to design and implement.
6. Instruction Pipeline: The simplicity and regularity of RISC instructions for make them well-suited pipelining. Instruction pipelining
allows multiple instructions to be processed simultaneously at different stages, improving performance.
7. Compiler-Dependent Optimization: RISC relies heavily on the compiler to optimize code and make use of the simple instruction set.
Since the instructions are simple, the compiler has to generate efficient code that takes advantage of the architecture.
Advantages

 Faster Execution
 Simpler Hardware Design
 Better Pipelining
 Energy Efficiency
Disadvantages
 Larger Code Size
 More Work for Compiler
 Memory Traffic
RISC vs CISC architecture
RISC CISC
Focus on software Focus on hardware
Uses only Hardwired control unit Uses both hard wired and microprogrammed
control unit
Transistors are used for more registers Transistors are used for storing complex
Instructions
Fixed sized instructions Can perform only Variable sized instructions Can perform REG
Register to Register Arithmetic operations to REG or REG to MEM or MEM to MEM
Code size is large Code size is small
An instruction executed in a single clock Instruction takes more than one clock cycle
cycle
The no. of instructions is less as compared to The no. of Instructions is more as compared
CISC to RISC.
VLIW Vs Superscalar Processor

VLIW Architecture Superscalar Processor

VLIW Architecture receives single multi- Superscalar processor except for a traditional
operation instruction. sequential flow of instruction but it can issue
multiple instructions.
VLIW architecture processors expect Superscalar processors do not expect
dependency-free code. dependency-free code to deal with
dependencies using special hardware
VLIW is less complex. Superscalar processors with the same degree
of parallelism are more complex than VLIW
architecture.
Instruction Formats

 An Instruction Format defines the structure and layout of an

instruction in a CPU’s instruction set. It specifies how the instruction is
encoded in binary and interpreted by the processor.
 Components of an Instruction Format:
1. Opcode (Operation Code) – Specifies the operation to be performed (e.g., ADD,
MOV).
2. Operands – Specifies the data or memory location(s) involved in the operation.
3. Addressing Mode – Defines how the operands are accessed (registers, memory,
immediate values).
Classification of Instructions
1. Based on operand types.

 The instruction set of a CPU typically includes the following categories:

(i) Data Transfer Instructions
 These instructions move data between registers, memory, and
input/output devices.
● MOV – Transfer data from one location to another
● LOAD (LD) – Load data from memory into a register
● STORE (ST) – Store data from a register to memory
● PUSH/POP – Move data to/from the stack
(ii) Arithmetic Instructions
 Used for mathematical operations.
● ADD – Addition
● SUB – Subtraction
● MUL – Multiplication
● DIV – Division
● INC/DEC – Increment/Decrement
(iii) Logical Instructions
 Perform bitwise and logical operations.
● AND – Logical AND operation
● OR – Logical OR operation
● XOR – Exclusive OR operation
● NOT – Logical negation
(iv) Control Transfer (Branching) Instructions
 Used for decision-making and loops.
● JMP – Jump to another instruction
● CALL/RET – Call and return from a subroutine
● JE (Jump if Equal), JNE (Jump if Not Equal), JG (Jump if Greater), JL (Jump if
Less) – Conditional jumps
(v) Input/Output Instructions
 Allow communication with external devices.
● IN – Read data from an input port
● OUT – Send data to an output port
 (vi) Special Purpose Instructions
● NOP (No Operation): CPU does nothing for one cycle.
● HLT (Halt): Stops CPU execution.
Types of Instruction Formats

 Different CPU architectures use different instruction formats.

The most common types are:
(i) Zero-Address Instructions
● No explicit operands; operates on an implicit stack.
● Example: PUSH, POP, ADD (in Stack-based machines)
(ii) One-Address Instructions
● One operand is specified; the other is stored in an accumulator.
● Example: ADD A (adds A to the accumulator)
(iii) Two-Address Instructions
● Both source and destination operands are specified.
● Example: MOV A, B (copies B into A)
(iv) Three-Address Instructions
● Three operands are explicitly mentioned, useful for complex calculations.
● Example: ADD A, B, C (A = B + C)
(v) Variable-Length Instructions
● Instruction length varies based on the operation and addressing mode.
● Found in Complex Instruction Set Computing (CISC) processors.
(vi) Fixed-Length Instructions
● Every instruction has the same length (e.g., 32-bit).
● Common in Reduced Instruction Set Computing (RISC) processors.
Instruction Set Architectures (ISA)

 There are two primary types of ISAs:

(i) Complex Instruction Set Computing (CISC)
● Uses a large and complex set of instructions.
● Fewer lines of assembly code required.
● Examples: Intel x86, AMD processors.
(ii) Reduced Instruction Set Computing (RISC)
● Uses a small and optimized set of instructions.
● Requires more instructions for complex operations but executes them faster.
● Examples: ARM, RISC-V processors.
Addressing Modes

 Addressing modes determine how the operand is accessed:

1. Immediate Addressing: Operand is directly specified in the instruction.
o Example: MOV R1, #5 (Move 5 to R1)
2. Register Addressing: Operand is stored in a register.
o Example: MOV R1, R2 (Copy value of R2 to R1)
3. Direct Addressing: Operand is stored in a memory location specified in the instruction.
o Example: MOV R1, [500H] (Load value from memory location 500H into R1)
4. Indirect Addressing: Operand address is stored in a register.
o Example: MOV R1, [R2] (Load value from memory address stored in R2 into R1)
5. Indexed Addressing: The operand address is calculated using a base address and an offset.
o Example: MOV R1, [R2 + 4]
6. Base Register Addressing: Similar to indexed addressing, but the register holds the base address, and the
instruction might include an offset.
Example: MOV R1, [R2 + R3] (move the value at the address formed by adding R2 and R3 into R1)
Based on the Processor's architecture:

 Depending on the processor's design, instructions can vary, but they generally fall into
these categories:
 CISC (Complex Instruction Set Computing): CPUs with a large number of complex
instructions, often involving multiple operands or addressing modes in a single
instruction.
Example: x86 architecture.
 RISC (Reduced Instruction Set Computing): CPUs with a smaller set of simpler
instructions, typically involving fewer operands and addressing modes.
Example: ARM, MIPS architectures.
Assembly Language

Definition:
 Assembly Language is a low-level programming language that uses
human-readable mnemonics instead of binary machine code. It
provides direct control over CPU operations.
 Features of Assembly Language:
● Uses mnemonics like MOV, ADD, SUB instead of binary codes.
● Requires an Assembler to convert assembly code into machine code.
● Allows direct memory and register manipulation.
● Faster than high-level languages but harder to code
 Advantages of Assembly Language:
❖ Efficient and fast execution.
❖ Direct Hardware Control
❖ Suitable for system Programming (OS,drivers)
 Disadvantages of Assembly Language:
❖ Difficult to learn compared to high-level languages.
❖ Machine-dependent (not portable).
Basic Assembly Language
Instructions

 Data Transfer Instructions:

Data transfer instructions are a category of CPU instructions used to move data between registers,
memory, and input/output devices.
• MOV destination, source - Moves data from the source to the destination.
For example MOV AX, 5
moves the constant value 5 into the AX register.
• PUSH operand- Pushes a value onto the stack.
For example PUSH AX
push the value in AX onto the stack
• POP destination - Pops a value from the stack.
For example POP AX – Pop the value from the stack into the AX register.
 LEA destination, source - Loads the address of the operand ('effective address') into the
destination register.
Eg: LEA AX, [BX+4] - load the address (BX + 4) into AX
 XCHG operand1, operand2 - Exchanges the values of two operands.
Eg: XCHG AX, BX swaps the values between the AX and BX registers.
 IN destination, port - Reads data from the specified I/O port and stores it in the destination
register.
Eg: IN AL, 60h - reads data from port 0x60 into the AL register.
 OUT port, source-Sends the value from the source register to the specified I/O port.
Eg: OUT 60h,AL - outputs the value in AL to port 0x60.
Arithmetic Instructions

 Arithmetic instructions are a category of CPU instructions used to perform basic

arithmetic operations, such as addition, subtraction, multiplication, and division, on data
stored in registers or memory. These operations are fundamental to most computations
performed by a computer.
1. ADD destination, source - Adds the source value to the destination register.
Example - ADD AX, BX
2. SUB destination, source - Subtracts the source value from the destination register.
Example - SUB AX, BX
 MUL operand - Multiplies the accumulator (AX for 16- bit operands) by the operand,
and stores the result in a pair of registers.
example: MUL BX
multiplies the value in AX by BX and stores the result in AX (16-bit
multiplication).
 DIV operand - Used for unsigned division. It divides the value in the accumulator
register by the operand, storing the quotient and remainder in separate registers.
example: DIV BX
divides the value in AX by BX, placing the quotient in AX and the remainder in DX.
 INC operand -Increments the value of the operand(register or memory) by 1. example: INC AX
the value in register AX is increased by 1.
 DEC operand-Decrements the value of the operand(register or memory) by 1.
example: DEC AX
Here, the value in register AX is decreased by 1.
 IMUL destination, source - Multiplies the destination register by the source operand and stores the
result in the destination register or pair of registers.
example: IMUL AX, BX - multiplies AX by BX using signed values and stores the result in AX.
 IDIV operand - Divides the value in the accumulator register by the operand, using signed values. The
quotient is stored in the accumulator, and the remainder is stored in the DX (16-bit) .
example : IDIV BX divides the signed value in AX by BX and stores the quotient in AX and the
remainder in DX.
 NEG operand - Negates the operand, changing its sign (positive to negative, or negative to positive).
example : NEG AX Here, the value in AX is negated (if it was positive, it becomes negative, and vice
versa).
Control Flow Instructions
 Control flow instructions in assembly language are used to alter the sequence of execution of a program, allowing for
decisions, loops, and the execution of specific sections of code based on certain condition.
 1. Unconditional Jump Instructions
Unconditional jumps allow the program to move to a different instruction, regardless of any conditions.
1. JMP destination - The JMP instruction unconditionally transfers control to a different part of the program, specified
by a label or address.
 For example: JMP label
 The program will always jump to the label, skipping any instructions in between.
2. CALL Subroutine -The CALL instruction is used to call a subroutine (function or procedure).
 It saves the return address on the stack, so the program can return to that address after the subroutine finishes.
 For example: CALL myFunction - program jumps to the myFunction subroutine, and the address of the next
instruction after CALL is pushed onto the stack
3. RET – RET instruction used to return from a subroutine. It pops the return address from the stack and jump into that
address.
Conditional Jump instructions

 Conditional jump instructions transfer control based on the status of flags in the CPU (such as Zero
Flag, Carry Flag, etc.). These flags are affected by previous operations like ADD, SUB, CMP, etc.
1. JE destination or JZ destination - These instructions jump to a specified label if the Zero Flag (ZF)
is set,indicating that the last comparisonresulted in zero.
 For example: JE label
2. JNZ destination –These instructions jump to the specified label if the Zero Flag (ZF) is clear,
meaning the result of the previous operation was not zero.
 For example: JNE label; Jump if Zero Flag is not set (notequal)
3. JC destination - The JC instruction jumps if the Carry Flag (CF) is set, indicating that the previous
operation caused a carry (e.g., in an unsigned addition or subtraction).
For example, JC label
 JL destination -The JL instruction jumps if the first operand is less than the second
operand, based on signed comparison.
For example:JL label
 JGE destination -The JGE instruction jumps if the previous comparison indicated that
the first operand is greater than or equal to the second operand, considering signed values.
For example:JGE label
 JLE destination -The JLE instruction jumps if the previous comparison showed that the
first operand is less than or equal to the second operand, considering signed values.
For Example:JLE label
Comparison Instructions

 Comparison instructions in assembly language are used to compare two operands and set
the status flags (Zero Flag, Carry Flag, Sign Flag, etc.) based on the result of the
comparison
Example - CMP AX, BX
✓ If AX == BX, the Zero Flag (ZF) will be set.
✓ If AX> BX, the Carry Flag (CF) will be cleared.
✓ If AX < BX, the Carry Flag (CF) will be set.
Logical Instructions

 AND A, B – Perform bitwise AND on A and B.

 OR A, B – Perform bitwise OR on A and B.
 XOR A, B – Perform bitwise XOR on A and B.
Shift and Rotate Instruction

 Shift and rotate instructions are used to shift or rotate the bits of a register or memory
operand. These operations are used for arithmetic or logic operations such as division, and
bit manipulation.
1. SHL operand, count - The SHL (Shift Left) instruction shifts the bits of the operand to the
left by a specified number of positions. The vacant bit positions on the right are filled with
zeros.
 For example: SHL AX, 1 ; Shift the bits of AX to the left by 1 position (multiply by 2)
2. SHR operand, count - The SHR (Shift Right) instruction shifts the bits of the operand to
the right by a specified number of positions. The vacant bit positions on the left are filled
with zeros.
 Example : SHR AX, 1 ; Shift the bits of AX to the right by 1 position.
 3. SAL operand, count
SAL (Shift Arithmetic Left) is essentially the same as SHL and shifts the bits of the operand
to the left.
For example: SAL AX, 1
4. SAR operand, count - The SAR (Shift Arithmetic Right) shifts the bits of the operand to
the right by a specified number of positions, but it preserves the sign bit for signed numbers.
SAR AX, 1 ; Shift AX right by 1 position
5. ROL operand, count
 The ROL (Rotate Left) instruction rotates the bits of the operand to the left by a specified
number of positions. The leftmost bit is moved to the rightmost position.
For example: ROL AX, 1 ; Rotate the bits of AX to the left by 1 position
6. ROR operand, count
 The ROR (Rotate Right) instruction rotates the bits of the operand to the right by a
specified number of positions.
Example- ROR AX,1
Example of Assembly Language Program

 Example: Adding Two Numbers

Assembly:
MOV AL, 05H ; Load 5 into AL register
MOV BL, 03H ; Load 3 into BL register
ADD AL, BL ; Add BL to AL
MOV CL, AL ; Store result in CL
Explanation:
1. MOV AL, 05H – Load the value 5 into register AL.
2. MOV BL, 03H – Load the value 3 into register BL.
3. ADD AL, BL – Add BL to AL (Result: AL = 8).
4. MOV CL, AL – Store the result in CL.
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