* Saturable Core Model, copied from:
* _SPICE Models For Power Electronics_, Meares and Hymowitz.
* 
.SUBCKT INDSAT 1 2 PARAMS: VSEC=1e-4 LMAG=1e-5 LSAT=1e-7 FEDDY=1e6
F1 1 2 VM1 1.0

*F11 2 11 VM1 1.0
*VM11 12 2 0.0
*R11 11 12 1.0
*C11 11 111 0p
*R111 111 2 0.2

G2 2 3 1 2 1.0
E1 4 2 3 2 1.0
VM1 4 5 0.0
RX 3 2 1E9
CB 3 2 {VSEC/500} IC=0
RB 5 2 {LMAG*500/VSEC}
RS 5 6 {LSAT*500/VSEC}
VP 7 2 250
VN 2 8 250
D1 6 7 DCLAMP
D2 8 6 DCLAMP
.MODEL DCLAMP D ( CJO={3*VSEC/(6.28*FEDDY*500*LMAG)} VJ=25 M=0.01 RS={LSAT/VSEC} )
.ENDS