This project generates advanced hardware design problems suitable for a Verilog programming contest. The problems are designed to push participants to demonstrate in-depth knowledge of digital logic, hardware architecture, timing analysis, and verification skills.

• .env: Environment variables for the project.
• .gitignore: Specifies files and directories to be ignored by Git.
• generate_verilog_codes.py: Python script to generate Verilog codes.
• LICENSE: License information for the project.
• README.md: This file, providing an overview of the project.
• DATA/: Directory containing task files.

1. Clone the repository:

   git clone https://github.com/yourusername/Verilog_Codes.git
   cd Verilog_Codes

2. Install dependencies:

   pip install -r requirements.txt

3. Create a .env file:

   echo "OLLAMA_API_URL=http://localhost:11434" > .env

1. Generate tasks and save them:

   python generate_verilog_codes.py

2. Generate reports for the saved task files:

   python generate_verilog_codes.py

Contributions are welcome! Please read the CONTRIBUTING.md for guidelines.

This project is licensed under the terms specified in the LICENSE file.