Watchy - An Open Source E-Ink Smartwatch

A comprehensive collection of cheatsheets for reverse engineering, binary analysis, and assembly programming tools. This repository serves as a one-stop reference for security researchers, reverse …

SEGGER RTT Sources

RISC-V Open Source Supervisor Binary Interface

An inhouse RISC-V 32-bits CPU

24 channel, 100Msps logic analyzer hardware and software

Linux kernel source tree

My dumping grounds for all my kicad projects and random hardware bringup.

Writing an OS in 1,000 lines.

Courses and some other useful resources to teach oneself a university degree in CS

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Build your hardware, easily!

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU G…

A curated learning repository focused on High-Performance Computing (HPC) — covering fundamentals to advanced topics in CUDA, MPI, C++, and Python-C++ interoperability.

Low-Level Programming Roadmap and Resources

Small and low cost FPGA educational and development board

Secure boot for 32-bit Microcontrollers!

RISC-V SoC designed by students in UCAS

Berkeley's Spatial Array Generator

Machine Learning inference engine for Microcontrollers and Embedded devices

Random instruction generator for RISC-V processor verification

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Windows Subsystem for Linux

Generic automation framework for acceptance testing and RPA

The source for the Linux kernel used in Windows Subsystem for Linux 2 (WSL2)

Learn AI/ML for beginners with a roadmap and free resources.

🤘 TT-NN operator library, and TT-Metalium low level kernel programming model.

A little fail-safe filesystem designed for microcontrollers

An open source bootloader for the PineTime based on MyNEWT and MCUBoot.