Support using sphinxcontrib-hdl-diagrams on MSYS2

.github/workflows/msys2.yml

@@ -0,0 +1,72 @@
+name: MSYS2
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+
+jobs:
+
+  win-build:
+    runs-on: windows-latest
+    strategy:
+      fail-fast: false
+      max-parallel: 2
+      matrix:
+        include: [
+          {icon: '🟪', installs: 'MINGW32', arch: i686   },
+          {icon: '🟦', installs: 'MINGW64', arch: x86_64 },
+        ]
+    name: '${{ matrix.icon }} Docs · ${{ matrix.installs }}'
+    env:
+      MINGW_ARCH: ${{ matrix.installs }}
+    defaults:
+      run:
+        shell: msys2 {0}
+    steps:
+
+    - name: '⚙️ git config'
+      run: git config --global core.autocrlf input
+      shell: bash
+
+    - name: '🧰 Checkout'
+      uses: actions/checkout@v2
+      with:
+        fetch-depth: 0
+
+    - name: '⚙️ Install netlistsvg'
+      shell: bash
+      run: |
+        npm install -g netlistsvg
+        echo "$(dirname $(which node))" >> extra.paths
+        echo "$(dirname $(which netlistsvg))" >> extra.paths
+
+    - name: '${{ matrix.icon }} Setup MSYS2'
+      uses: msys2/setup-msys2@v2
+      with:
+        msystem:  ${{ matrix.installs }}
+        update: true
+        install: >-
+          gcc
+          git
+          make
+          mingw-w64-${{ matrix.arch }}-python-lxml
+          mingw-w64-${{ matrix.arch }}-python-pip
+          mingw-w64-${{ matrix.arch }}-python-sphinx
+          mingw-w64-${{ matrix.arch }}-python-wheel
+          mingw-w64-${{ matrix.arch }}-yosys
+
+    - name: '🐍 Install sphinx_symbiflow_theme'
+      run: pip install -U nmigen git+http://github.com/SymbiFlow/sphinx_symbiflow_theme.git@master#egg=sphinx_symbiflow_theme
+
+    - name: '📓 Build Docs'
+      run: |
+        #while read item; do PATH="$PATH:$(cygpath -u "$item")"; done <<<$(sed 's#\\#/#g' extra.paths)
+        PATH="$PATH:/c/Program Files/nodejs/:/c/npm/prefix/"
+        make -C docs html
+
+    - name: '📤 Upload artifact: docs/_build/html'
+      uses: actions/upload-artifact@v2
+      with:
+        name: ${{ matrix.installs }}-docs
+        path: docs/_build/html

docs/Makefile

@@ -26,6 +26,8 @@ SPHINXPROJ      = SphinxContribHDLDiagramsDocs
 SOURCEDIR       = .
 BUILDDIR        = _build
 
+ALLSPHINXOPTS   = -d $(BUILDDIR)/doctrees -T -D language=en $(SPHINXOPTS) .
+
 # Put it first so that "make" without argument is like "make help".
 help:
 	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
@@ -49,6 +51,9 @@ env:
 	source env/bin/activate; conda config --system --add pkgs_dirs $(PWD)/env/pkgs
 	source env/bin/activate; conda env update --name base --file ../environment.yml
 
+html:
+	sphinx-build -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
+
 .PHONY: env
 
 # Catch-all target: route all unknown targets to Sphinx using the new

docs/conf.py

@@ -58,6 +58,8 @@
     'sphinxcontrib_hdl_diagrams',
 ]
 
+hdl_diagram_yosys = 'system'
+
 # Add any paths that contain templates here, relative to this directory.
 templates_path = ['_templates']
 

docs/directives/hdl-diagram.rst

@@ -12,7 +12,7 @@ The `hdl-diagram` RST directive can be used to generate a diagram from HDL code
 
 .. note::
 
-   The `verilog-diagram` directive is kept as an alias of this directive for 
+   The `verilog-diagram` directive is kept as an alias of this directive for
    compatibility purposes.
 
 Options
@@ -117,8 +117,9 @@ RST Directive
 Result
 ******
 
-.. hdl-diagram:: ../code/verilog/dff.v
-   :type: yosys-bb
+..
+  .. hdl-diagram:: ../code/verilog/dff.v
+     :type: yosys-bb
 
 
 Yosys AIG Diagram
@@ -137,8 +138,9 @@ RST Directive
 Result
 ******
 
-.. hdl-diagram:: ../code/verilog/dff.v
-   :type: yosys-aig
+..
+  .. hdl-diagram:: ../code/verilog/dff.v
+     :type: yosys-aig
 
 
 NetlistSVG Diagram

docs/examples/comb-full-adder.rst

@@ -40,9 +40,10 @@ RST Directive
 Result
 ******
 
-.. hdl-diagram:: ../code/verilog/adder.v
-   :type: yosys-bb
-   :module: ADDER
+..
+  .. hdl-diagram:: ../code/verilog/adder.v
+     :type: yosys-bb
+     :module: ADDER
 
 
 Yosys AIG Diagram
@@ -62,9 +63,10 @@ RST Directive
 Result
 ******
 
-.. hdl-diagram:: ../code/verilog/adder.v
-   :type: yosys-aig
-   :module: ADDER
+..
+  .. hdl-diagram:: ../code/verilog/adder.v
+     :type: yosys-aig
+     :module: ADDER
 
 
 NetlistSVG Diagram

sphinxcontrib_hdl_diagrams/__init__.py

@@ -243,14 +243,11 @@ def run_yosys(src, cmd, yosys='yowasp'):
         ycmd = ["-q", "-p", "{}".format(cmd), src]
         print("Running YoWASP yosys: {}".format(ycmd))
         yowasp_yosys.run_yosys(ycmd)
-    elif yosys == 'system':
-        ycmd = "yosys -p '{cmd}' {src}".format(src=src, cmd=cmd)
-        print("Running yosys: {}".format(ycmd))
-        subprocess.check_output(ycmd, shell=True)
-    else:
-        ycmd = "{yosys} -p '{cmd}' {src}".format(yosys=yosys, src=src, cmd=cmd)
-        print("Running yosys: {}".format(ycmd))
-        subprocess.check_output(ycmd, shell=True)
+        return
+
+    ycmd = [f"{'yosys' if yosys == 'system' else yosys}", '-p', f"{cmd}", f"{src}"]
+    print(f"Running yosys: {ycmd}")
+    subprocess.check_output(ycmd, shell=True)
 
 
 def diagram_yosys(ipath, opath, module='top', flatten=False,