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  1. verilog-parser verilog-parser Public

    Forked from ben-marshall/verilog-parser

    A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.

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  2. Basic-SIMD-Processor-Verilog-Tutorial Basic-SIMD-Processor-Verilog-Tutorial Public

    Forked from zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

    Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …

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  3. USTC-RVSoC USTC-RVSoC Public

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    An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。

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  4. learning-systemVerilog learning-systemVerilog Public

    Forked from yuxiang660/learning-systemVerilog

    learning notes of SystemVerilog与功能验证

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  5. risc-v-processor-sv risc-v-processor-sv Public

    Forked from pastchick3/risc-v-processor-sv

    A simple RISC-V processor for learning, written in SystemVerilog.

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  6. bch_verilog bch_verilog Public

    Forked from russdill/bch_verilog

    Verilog based BCH encoder/decoder

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