add UVM intro

Author: yuxiang660

UVMTutorial.md

@@ -3,4 +3,15 @@
 
 # UVM TestBench 和 SystemVerilog TestBench 对比
 ![UVM](./code/uvm-tb.gif)
+* [DUT](./code/uvm-tb/dut_wrapper.sv)
+    - 被测试电路，接口由interface定义
+* [Interface](./code/uvm_tb/dut_if.sv)
+    - 接口定义，所有组件和DUT交流，都通过此interface
+* [Environment](./code/uvm_tb/my_pkg.sv)
+    - 测试的环境组件，会在其中创建所有相关组件，包括：Driver, Monitor, Scoreboard等
+* [Test](./code/uvm_tb/test_pkg.sv)
+    - 配置测试，此组件会实现各种测试的不同配置
+* [Top](./code/uvm_tb/tb_top.sv)
+    - top level module, 启动测试
 
+![TB](./code/testbenchComponent.png)

code/uvm-tb/Makefile

@@ -0,0 +1,11 @@
+TARGET=tb_top.sv
+SCRIPT=compile.do
+
+all : $(TARGET) $(SCRIPT)
+	vsim -do $(SCRIPT)
+
+.PHONY: clean
+
+clean:
+	rm -f transcript
+	rm -rf work

code/uvm-tb/compile.do

@@ -0,0 +1,5 @@
+set UVM_DPI_HOME C:/modeltech64_10.1c/uvm-1.1/win64
+vlib work
+vlog -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF timescale.v dut_if.sv dut_wrapper.sv my_pkg.sv test_pkg.sv tb_top.sv
+vsim -c -novopt -sv_lib $UVM_DPI_HOME/uvm_dpi work.top
+run

code/uvm-tb/dut_if.sv

@@ -0,0 +1,10 @@
+`include "timescale.v"
+
+interface dut_if (input clk);
+  logic          rstn;
+  logic [7:0]    wdata;
+  logic [7:0]    rdata;
+  logic [7:0]    addr;
+  logic          wr;
+  logic          en;
+endinterface

code/uvm-tb/dut_wrapper.sv

@@ -0,0 +1,25 @@
+`include "timescale.v"
+
+module dut (   
+  input    clk,                 // Clock at some freq
+  input    rstn,                // Active Low  Sync Reset
+  input    wr,                  // Active High Write
+  input    en,                  // Module Enable
+  input    wdata,               // Write Data
+  input    addr,                // Address
+
+  output   rdata                // Read Data
+);
+// Empty module
+endmodule
+
+module dut_wrapper (dut_if _if);
+  // Instantiate the design module and connect interface signals to DUT
+  dut dsn0     (  .clk     (_if.clk),
+                    .rstn    (_if.rstn),
+                    .wr      (_if.wr),
+                    .en      (_if.en),
+                    .wdata   (_if.wdata),
+                    .addr    (_if.addr),
+                    .rdata   (_if.rdata));
+endmodule

code/uvm-tb/my_pkg.sv

@@ -0,0 +1,27 @@
+`include "uvm_macros.svh"
+ 
+package my_pkg;
+  // If you don't use this, it'll complain that it doesn't recognize uvm components
+  import uvm_pkg::*;
+
+  //---------------------------------------------------------------------------------------------------------------------
+  //                                                 my_env
+  //---------------------------------------------------------------------------------------------------------------------
+  class my_env extends uvm_env ;
+    `uvm_component_utils (my_env)
+
+    function new (string name, uvm_component parent);
+        super.new (name, parent);
+    endfunction : new
+
+    function void build_phase (uvm_phase phase);
+        super.build_phase (phase);
+    endfunction : build_phase
+
+    task run_phase (uvm_phase phase);
+        set_report_verbosity_level (UVM_MEDIUM);
+        uvm_report_info      (get_name(), $sformatf ("Hello UVM ! Simulation has started."), UVM_MEDIUM, `__FILE__, `__LINE__);
+        `uvm_info   (get_name(), $sformatf("Finishing up with run_phase ... "), UVM_LOW)
+    endtask : run_phase
+  endclass : my_env
+endpackage

code/uvm-tb/tb_top.sv

@@ -0,0 +1,29 @@
+`include "timescale.v"
+
+module top;
+  import uvm_pkg::*;
+  import test_pkg::*;
+
+//-----------------------------------------------------------------------------
+// Clock Generation Module; Flips every 10ns => Freq = 50 MHz 
+//-----------------------------------------------------------------------------
+  bit clk;
+  always #10 clk <= ~clk; 
+
+//-----------------------------------------------------------------------------
+// Instantiate the Interface and pass it to Design Wrapper
+//-----------------------------------------------------------------------------
+  dut_if         dut_if1  (clk);
+  dut_wrapper    dut_wr0  (._if (dut_if1));
+
+//-----------------------------------------------------------------------------
+// At start of simulation, set the interface handle as a config object in UVM 
+// database. This IF handle can be retrieved in the test using the get() method
+// run_test () accepts the test name as argument. In this case, base_test will
+// be run for simulation
+//-----------------------------------------------------------------------------
+  initial begin
+    uvm_config_db #(virtual dut_if)::set (null, "uvm_test_top", "dut_if", dut_if1);
+    run_test ("base_test");
+  end
+endmodule

code/uvm-tb/test_pkg.sv

@@ -0,0 +1,76 @@
+`include "uvm_macros.svh"
+
+package test_pkg;
+  import uvm_pkg::*;
+  import my_pkg::*;
+
+  //---------------------------------------------------------------------------------------------------------------------
+  //                                                 base_test   {{{1
+  //---------------------------------------------------------------------------------------------------------------------
+
+  class base_test extends uvm_test;
+
+    `uvm_component_utils (base_test)
+
+    my_env   m_top_env;
+    virtual  dut_if dut_vi;
+
+    function new (string name, uvm_component parent = null);
+        super.new (name, parent);
+    endfunction : new
+
+    virtual function void build_phase (uvm_phase phase);
+        super.build_phase (phase);
+
+        // Instead of using new to creat my_env, type_id::create is the preferred way because it uses factory methods
+        m_top_env  = my_env::type_id::create ("m_top_env", this);
+
+        // setting and retrieving variable values in UVM
+        // get the dut_if object form the database
+        if (! uvm_config_db #(virtual dut_if) :: get (this, "", "dut_if", dut_vi)) begin
+          `uvm_error (get_type_name (), "DUT Interface not found !")
+        end
+        else
+          `uvm_info (get_type_name (), "DUT Interface is found !", UVM_LOW)
+    endfunction : build_phase
+
+    virtual function void end_of_elaboration_phase (uvm_phase phase);
+        `uvm_info (get_type_name (), "end_of_elaboration_phase", UVM_LOW)
+        uvm_top.print_topology ();
+    endfunction
+
+    function void start_of_simulation_phase (uvm_phase phase);
+        `uvm_info (get_type_name (), "start_of_simulation_phase", UVM_LOW)
+        super.start_of_simulation_phase (phase);
+    endfunction
+
+  endclass 
+
+  //---------------------------------------------------------------------------------------------------------------------
+  //                                                 reg_test   {{{1
+  //---------------------------------------------------------------------------------------------------------------------
+
+  class reg_test extends base_test;
+    `uvm_component_utils (reg_test)
+
+    function new (string name, uvm_component parent = null);
+        super.new (name, parent);
+    endfunction
+
+    // Enter your test for register access here
+  endclass
+
+  //---------------------------------------------------------------------------------------------------------------------
+  //                                                 feature_test   {{{1
+  //---------------------------------------------------------------------------------------------------------------------
+
+  class feature_test extends base_test;
+    `uvm_component_utils (feature_test)
+
+    function new (string name, uvm_component parent = null);
+        super.new (name, parent);
+    endfunction 
+    // Enter test code for feature here
+  endclass
+
+endpackage : test_pkg

code/uvm-tb/timescale.v

@@ -0,0 +1 @@
+`timescale 1ns/1ps