add simple testbench demo

Author: yuxiang660

.gitignore

@@ -5,4 +5,7 @@
 transcript
 
 # waveform file
-*.wlf
+*.wlf
+
+# waveform output
+*.vcd

SystemVerilogTutorial.md

@@ -37,3 +37,36 @@
     包括所有的测试环境
 ![testbench](./code/testbenchComponent.png)
 
+## 什么是DUT？
+* DUT全称"Design Under Test"，是被测的硬件电路。在仿真测试中，DUT也称为DUV，即"Design Under Verification"。
+* [例子 dut.v](./code/testbench/dut.v)
+
+## 什么是interface？
+* 当DUT的端口非常复杂时，可通过定义interface抽象出测试关心的输入输出端口。
+* [例子 interface.sv](./code/testbench/interface.sv)
+
+## 什么是driver？
+* driver定义了一个task用于驱动输入信号到被测电路，可被其他模块调用。
+* [例子 driver.sv](./code/testbench/driver.sv)
+
+## driver如何实现驱动？
+* generator生成有效的数据([data transaction](./code/testbench/data.sv))给driver，driver再将数据传输到被测电路。
+* 例子"testbench"中并没有generator，generator的行为被放入了test组件。
+
+## 为什么需要monitor？
+* driver会将数据输入给DUT执行，monitor会获取DUT的输出信号，并将其传给scoreboard和期望数据做比较。
+* [例子 monitor.sv](./code/testbench/scoreboard.sv)
+
+## scoreboard的目的是什么？
+* scoreboard内部有一个和DUT行为一样的`reference model`。driver输入给DUT的信号同时会输入给scoreboard，此输入经过scoreboard中的`reference model`会产生DUT的期望输出。`reference model`的输出应该和monitor传过来的数据一致，否则测试失败。
+* [例子 scoreboard.sv](./code/testbench/scoreboard.sv)
+
+## 为什么需要environment？
+* environment组件是为了增加testbench的可扩展性，可在其中加入更过其他的组件。
+* [例子 environment.sv](./code/testbench/environment.sv)
+
+## test组件是做什么的？
+* test会实例化一个environment组件，并实施配置。
+
+## testbench流程是如何的？
+* Generator -> Driver -> Interface -> Design -> Interface -> Monitor -> Scoreboard

code/testbench/data.sv

@@ -0,0 +1,16 @@
+// This is the base transaction object that will be used
+// in the environment to initiate new transactions and 
+// capture transactions at DUT interface
+class reg_item;
+    rand 	bit [7:0] 	addr;
+    rand 	bit [15:0] 	wdata;
+            bit [15:0] 	rdata;
+    rand 	bit 		wr;
+
+    // This function allows us to print contents of the data packet
+    // so that it is easier to track in a logfile
+    function void print(string tag="");
+        $display ("T=%0t [%s] addr=0x%0h wr=%0d wdata=0x%0h rdata=0x%0h", 
+                            $time, tag, addr, wr, wdata, rdata);
+    endfunction
+endclass

code/testbench/demo/Makefile

@@ -0,0 +1,11 @@
+TARGET=testbench.sv
+SCRIPT=compile.do
+
+all : $(TARGET) $(SCRIPT)
+	vsim -do $(SCRIPT)
+
+.PHONY: clean
+
+clean:
+	rm -f transcript vsim.wlf
+	rm -rf work

code/testbench/demo/compile.do

@@ -0,0 +1,5 @@
+set UVM_DPI_HOME C:/modeltech64_10.1c/uvm-1.1/win64
+vlib work
+vlog -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF design.sv testbench.sv
+vsim -c -novopt -sv_lib $UVM_DPI_HOME/uvm_dpi work.tb
+run

code/testbench/demo/design.sv

@@ -0,0 +1,74 @@
+// Note that in this protocol, write data is provided
+// in a single clock along with the address while read
+// data is received on the next clock, and no transactions
+// can be started during that time indicated by "ready"
+// signal.
+
+module reg_ctrl 
+  # (
+     parameter ADDR_WIDTH 	= 8,
+     parameter DATA_WIDTH 	= 16,
+     parameter DEPTH 		= 256,
+     parameter RESET_VAL  	= 16'h1234
+  )
+  ( input 					clk,
+  	input 					rstn,
+    input [ADDR_WIDTH-1:0] 	addr,
+    input 					sel,
+  	input 					wr,
+    input [DATA_WIDTH-1:0] 	wdata,
+    output reg [DATA_WIDTH-1:0] 	rdata,
+    output reg				ready);
+  
+  	// Some memory element to store data for each addr
+    reg [DATA_WIDTH-1:0] ctrl [DEPTH];
+  
+  reg  ready_dly;
+  wire ready_pe;
+  
+  // If reset is asserted, clear the memory element
+  // Else store data to addr for valid writes
+  // For reads, provide read data back
+  always @ (posedge clk) begin
+    if (!rstn) begin
+      for (int i = 0; i < DEPTH; i += 1) begin
+        ctrl[i] <= RESET_VAL;
+      end
+    end else begin
+    	if (sel & ready & wr) begin
+      		ctrl[addr] <= wdata;
+    	end
+ 
+    	if (sel & ready & !wr) begin
+          rdata <= ctrl[addr];
+  		end else begin
+          rdata <= 0;
+        end
+    end
+  end
+  
+  // Ready is driven using this always block
+  // During reset, drive ready as 1
+  // Else drive ready low for a clock low
+  // for a read until the data is given back
+  always @ (posedge clk) begin
+    if (!rstn) begin
+      ready <= 1;
+    end else begin
+      if (sel & ready_pe) begin
+      	ready <= 1;
+      end
+	 if (sel & ready & !wr) begin
+       ready <= 0;
+     end
+    end
+  end
+  
+  // Drive internal signal accordingly
+  always @ (posedge clk) begin
+    if (!rstn) ready_dly <= 1;
+   		else ready_dly <= ready;
+  end
+  
+   assign ready_pe = ~ready & ready_dly;
+endmodule