1 Release published by 1 person

• v0.5.5 0.5.5

  published May 12, 2025

13 Pull requests merged by 4 people

• Update changelog for v0.5.5 [v0.5.x backport]

  #1597 merged May 12, 2025

• Update changelog for v0.5.5

  #1598 merged May 12, 2025

• hdl._ir: chain Fragment.origins with preexisting [0.5 backport]

  #1594 merged May 12, 2025

• hdl._ir: chain Fragment.origins with preexisting

  #1593 merged May 12, 2025

• lib.wiring: make FlippedInterface hashable

  #1580 merged May 12, 2025

• sim: call .aclose() on TickTrigger in .until() and .repeat()

  #1590 merged May 11, 2025

• sim: call .aclose() on TickTrigger in .until() and .repeat() [0.5 backport]

  #1591 merged May 11, 2025

• backends: s/ilang/rtlil as a result of YosysHQ/yosys#4704

  #1575 merged May 6, 2025

• lib.wiring: make wiring.connect source locations accurate [0.5 backport]

  #1587 merged Apr 29, 2025

• lib.wiring: make wiring.connect source locations accurate

  #1586 merged Apr 29, 2025

• vendor._lattice: fix typo in clock constraint generation

  #1582 merged Apr 26, 2025

• vendor._lattice: fix typo in clock constraint generation [0.5 backport]

  #1583 merged Apr 26, 2025

• lib.wiring: make FlippedInterface hashable [0.5 backport]

  #1581 merged Apr 24, 2025

2 Pull requests opened by 2 people

• [WIP] Implement RFC 41: `lib.fixed`

  #1578 opened Apr 21, 2025

• CI: add pypy-3.11

  #1585 opened Apr 27, 2025

5 Issues opened by 4 people

• Tracking issue for RFC 74: Structured VCD Output

  #1599 opened May 13, 2025

• Tracking issue for RFC 76: `amaranth-boards` versioning policy.

  #1595 opened May 12, 2025

• Add a documentation URL alias that always points at the latest release

  #1592 opened May 11, 2025

• Vivado transparent memory issue

  #1589 opened May 1, 2025

• `convert` used with `Component` does not handle constant signals

  #1574 opened Apr 14, 2025