adrv9026/zcu102: Update build parameters

Signed-off-by: AndrDragomir <[email protected]>

Updates stingray next stable (#1482)

* projects/ad9081_fmca_ebz_x_band: Fix TDD sync

This commit changes the following:
- the RX TDD sync can be performed trough both the DO or DMAC
- the clock domain crossing is performed in the DMA instead of the DO
- the RX DMA LENGTH WIDTH was increased to allow large buffer captures
- library/axi_dmac/data_mover: Merge changes from main

Signed-off-by: PopPaul2021 <[email protected]>

docs: Add Imageon page

Signed-off-by: alin724 <[email protected]>

hdl: Zed-AD7768: Wideband fixed bug_2022_R2 (#1282)

* hdl: Zed-AD7768: Wideband fixed bug

In SPI control mode, when not used as GPIO the FILTER pin and when a crystal
is used as the clock source, this pin must be set to 1.
The START pin must be tied to a logic 1 through a pull-up resistor, when
it is not used.

Signed-off-by: Ioan-daniel Pop <[email protected]>

axi_ad7606x: Add the correct IP's name

Signed-off-by: Alin-Tudor Sferle <[email protected]>
(cherry picked from commit 03c4276)

Changed the default AD9081 profile for VCK190

* RX_mode=27, L=4, M=4, S=2, NP=12, Lane_rate=12.375 GHz
* TX_mode=23, L=4, M=4, S=2, NP=12, Lane_rate=12.375 GHz
* Ref_clk=375 MHz, Device_clk=125 MHz

ad4858_fmcz: add support for zcu102

The LVDS interface requires digital(delay) tuning by software.

util_do_ram: Fix Rx path for interrupted transfers

When capture length is not programmed the DMA will interrupt the
transfer once it received all the samples he was set in its descriptor,
this case must be handled by resetting the read process and returning
an end of transfer (eot) to the data offload control logic.

pluto: Fix dunf connection

USDRX1 ulstrasound hdl reference design