boards/intel_adsp_ace15_mtpm: Update google AEC kconfigs

Update defaults to match existing hardware.  The topologies currently
have four channels of S32_LE DMIC input, but AEC can only handle two
at runtime, so set it here to prevent it from allocating needless
buffers.

Also disable the mock setting, it's already selected by COMP_STUBS

Signed-off-by: Andy Ross <[email protected]>

ipc: header size validation fix

This patch will deny IPC headers with size 0

Signed-off-by: Adrian Bonislawski <[email protected]>

topology: fix a typo for SCHEDULE_CORE

With define for W_PCM_CAPTURE only need 5 arguments
W_PCM_CAPTURE(pcm, stream, periods_sink, periods_source, core)
Fix the wrong parameter in pipe-kfbm-capture.m4

Signed-off-by: Pan Xiuli <[email protected]>

topology: fix a typo for SCHEDULE_CORE

With define for W_PCM_CAPTURE only need 5 arguments
W_PCM_CAPTURE(pcm, stream, periods_sink, periods_source, core)
Fix the wrong parameter in pipe-kfbm-capture.m4

Signed-off-by: Pan Xiuli <[email protected]>

platform: intel: add clock switch for waiti

Platforms with cAVS version 1.8 & 2.0 have hardware requirement that
DSP should use LPRO as clock source in waiti.
This patch adds config for that and enables it for platforms that
need it.

Signed-off-by: Janusz Jankowski <[email protected]>

sof: audio: free memory before returning in error

Memory allocated for new KPB component should be released before
returning NULL in when one of sampling width or number of channels or
sampling frequency are set to unexpected values.

Signed-off-by: Deepak R Varma <[email protected]>

Topology: Add HDA config

We need to config HDA rate and channels.

Signed-off-by: Bard Liao <[email protected]>

apl: change dmic format to s32_le in sof-glk-da7219.tplg

In order to allow record s16_le/s24_le/s32_le format this
commit changes DAI component's and DMIC's format to s32_le
on PCM99.
In case recording s16_le/s24_le DAI component makes pcm
conversion from s16_le/s24_le to s32_le.

Signed-off-by: Bartosz Kokoszko <[email protected]>

drivers: imx: irqsteer: Fix computation of status

status of an output irqsteer line is a 64bit variable
composed of 2 x 32 bit registers.

Because first 64 output irqsteer lines only holds status for
IRQ in[0] we have a different formula for getting the status
compared to the existing implementation done for i.MX8QXP/i.MX8QM.

Mapping for status register is as follows:

line 0 -> [0 | chan0]
line 1 -> [chan2 | chan1]
line 3 -> [chan4 | chan 3]

Signed-off-by: Daniel Baluta <[email protected]>

sof: align sof structure to cache line size

Aligns sof structure to cache line size. It is needed
in order to assure that no data will be randomly overwritten
by cache eviction with multicore access.

Signed-off-by: Tomasz Lauda <[email protected]>