[linux-6.6.y]LoongArch Stage Patch Synchronization 0606 #865
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Reviewer's GuideThis patchset introduces comprehensive LoongArch support across GPU drivers, net, pwm, crypto, ACPI and SMP layers by adding new drivers, enabling multi-channel and multi-core capabilities, and implementing architecture-specific workarounds (e.g., cache-flush fixes in AMDGPU/radeon on LoongArch). Sequence Diagram: AMDGPU IH Cache Flush Workaround (LoongArch)sequenceDiagram
participant CS as amdgpu_cs_submit
participant IH_P as amdgpu_ih_process
participant IH_Ring_HW_Access
participant LoongArchFix as LoongArch_IH_Fix_Functions
participant WorkQueue
participant FixWork as amdgpu_ih_handle_fix_work
CS ->> LoongArchFix: amdgpu_ih_fix_is_busy(adev)
activate LoongArchFix
LoongArchFix -->> CS: is_busy_flag
deactivate LoongArchFix
alt IH fix is busy
CS ->> CS: msleep(20)
else IH fix not busy
CS ->> IH_P: amdgpu_ih_process(adev, ih)
activate IH_P
IH_P ->> IH_Ring_HW_Access: wptr = amdgpu_ih_get_wptr(adev, ih)
IH_P ->> LoongArchFix: r = amdgpu_ih_fix_loongarch_pcie_order_start(ih, old_rptr, wptr, false)
activate LoongArchFix
LoongArchFix -->> IH_P: r_status
deactivate LoongArchFix
alt r != 0 (needs fix work)
IH_P ->> WorkQueue: schedule_work(&adev->irq.ih.fix_work)
WorkQueue ->> FixWork: amdgpu_ih_handle_fix_work(work)
activate FixWork
FixWork ->> IH_Ring_HW_Access: wptr = amdgpu_ih_get_wptr(adev, ih)
FixWork ->> LoongArchFix: amdgpu_ih_fix_loongarch_pcie_order_start(ih, old_rptr, wptr, true)
loop Process ring
FixWork ->> IH_Ring_HW_Access: amdgpu_irq_dispatch(adev, ih)
end
FixWork ->> LoongArchFix: amdgpu_ih_fix_loongarch_pcie_order_end(ih, old_rptr, new_rptr)
FixWork ->> IH_Ring_HW_Access: amdgpu_ih_set_rptr(adev, ih)
FixWork ->> LoongArchFix: atomic_set(&adev->irq.cs_lock, 0)
deactivate FixWork
else r == 0 (no fix work needed or successful immediate fix)
loop Process ring
IH_P ->> IH_Ring_HW_Access: amdgpu_irq_dispatch(adev, ih)
end
IH_P ->> LoongArchFix: amdgpu_ih_fix_loongarch_pcie_order_end(ih, old_rptr, new_rptr)
IH_P ->> IH_Ring_HW_Access: amdgpu_ih_set_rptr(adev, ih)
end
deactivate IH_P
end
Sequence Diagram: WST Crypto SE Driver User Write OperationsequenceDiagram
actor User
participant VFS_CharDev as "Char Device Interface (se_userwrite)"
participant SE_Core as "SE Driver Core (se_hardtrans, workqueues)"
participant SE_HW_Access as "SE Hardware (MMIO/DMA)"
participant IRQ_Handler as "Interrupt Handler (se_interrupt)"
User->>VFS_CharDev: write(params, in_data)
activate VFS_CharDev
VFS_CharDev->>SE_Core: se_hardtrans(pdrvctl, pInPtr, usInlen, ...)
activate SE_Core
SE_Core->>SE_Core: Create ST_SEND_PACKAGE
SE_Core->>SE_Core: Add to g_SendQueueContainer
SE_Core->>SE_Core: queue_work(g_worksendqueue, &g_sendwork)
Note over SE_Core: globalmem_do_send_op (g_sendwork) runs:
SE_Core->>SE_HW_Access: Map DMA buffers (pInPtr, pOutPtr)
SE_Core->>SE_HW_Access: Prepare & Write BD to HW Ring
SE_Core->>SE_HW_Access: Update BD Write Pointer (BQWP0/1 via MMIO)
deactivate SE_Core
VFS_CharDev-->>User: (potentially returns if async or waits on completion)
deactivate VFS_CharDev
SE_HW_Access->>SE_HW_Access: SE Hardware processes BD, performs DMA & crypto op
SE_HW_Access-->>IRQ_Handler: Hardware Interrupt (DMA_PACK_DONE)
activate IRQ_Handler
IRQ_Handler->>SE_HW_Access: Read Status & BD Read Pointer (RQRP0/1 via MMIO)
IRQ_Handler->>SE_HW_Access: Clear Interrupt (INT_CLR via MMIO)
Note over IRQ_Handler: Process completed BDs
IRQ_Handler->>SE_HW_Access: Unmap DMA buffers
alt User-space call (synchronous)
IRQ_Handler->>VFS_CharDev: complete(mycomplete)
else Kernel callback (asynchronous)
IRQ_Handler->>SE_Core: Create ST_INT_MESSAGE, add to g_RecQueueContainer
IRQ_Handler->>SE_Core: queue_work(g_workrecqueue, &g_recwork)
activate SE_Core
Note over SE_Core: globalmem_do_rec_op (g_recwork) runs callback
deactivate SE_Core
end
deactivate IRQ_Handler
Class Diagram: AMDGPU IH/IRQ LoongArch AdditionsclassDiagram
direction LR
class amdgpu_ih_ring {
+struct work_struct fix_work
+void *ring
+u32 rptr
+u32 wptr
+unsigned int ptr_mask
+wait_queue_head_t wait_process
+u64 processed_timestamp
}
class amdgpu_irq {
+atomic_t cs_lock
+spinlock_t lock
+bool msi_enabled
+struct amdgpu_ih_ring ih
+struct amdgpu_ih_ring ih1
+struct amdgpu_ih_ring ih_soft
#List of other fields...
}
class amdgpu_device {
+struct amdgpu_irq irq
+bool shutdown
#List of other fields...
}
amdgpu_device "1" *-- "1" amdgpu_irq : aggregates
amdgpu_irq "1" *-- "1..*" amdgpu_ih_ring : aggregates
class LoongArch_IH_Functions {
<<module: amdgpu_ih.c>>
+amdgpu_ih_handle_fix_work(struct work_struct *work) void
+amdgpu_ih_fix_loongarch_pcie_order_start(struct amdgpu_ih_ring *ih, u32 rptr, u32 wptr, bool forever) int
+amdgpu_ih_fix_loongarch_pcie_order_end(struct amdgpu_ih_ring *ih, u32 rptr, u32 wptr) int
+amdgpu_ih_fix_is_busy(struct amdgpu_device *adev) int
}
LoongArch_IH_Functions ..> amdgpu_ih_ring : uses
LoongArch_IH_Functions ..> amdgpu_device : uses
Class Diagram: Loongson GMAC Multi-Channel SupportclassDiagram
direction LR
class loongson_data {
+u32 multichan
+u32 loongson_id
+struct device *dev
}
class plat_stmmacenet_data {
+int bus_id
+int phy_addr
+struct mac_device_info *mac_plat_data
+int rx_queues_to_use
+int tx_queues_to_use
+struct stmmac_rxq_cfg tx_queues_cfg[]
+void *bsp_priv
}
plat_stmmacenet_data "1" *-- "1" loongson_data : "bsp_priv points to"
class Loongson_GMAC_Functions {
<<module: dwmac-loongson.c>>
+loongson_default_data(pdev, plat) void
+loongson_dwmac_msi_config(pdev, plat, res) int
+loongson_dwmac_setup(apriv) mac_device_info*
+loongson_dwmac_probe(pdev, id) int
}
Loongson_GMAC_Functions ..> loongson_data : uses
Loongson_GMAC_Functions ..> plat_stmmacenet_data : configures
Class Diagram: Loongson PWM DriverclassDiagram
direction LR
class pwm_loongson_ddata {
+struct pwm_chip chip
+struct clk *clk
+void __iomem *base
+u64 clk_rate
}
class pwm_chip {
+struct device *dev
+struct pwm_ops *ops
+int npwm
#List of other fields...
}
pwm_loongson_ddata "1" *-- "1" pwm_chip : "contains"
class Loongson_PWM_Ops {
<<pwm_ops>>
+apply(chip, pwm, state) int
+get_state(chip, pwm, state) int
#enable, disable, config are part of apply
}
pwm_chip ..> Loongson_PWM_Ops : uses
class Loongson_PWM_Functions {
<<module: pwm-loongson.c>>
+pwm_loongson_probe(pdev) int
#Internal functions like pwm_loongson_enable, etc.
}
Loongson_PWM_Functions ..> pwm_loongson_ddata : creates & manages
Class Diagram: WST Crypto SE Driver Core StructuresclassDiagram
direction LR
class tagSEdrvctl {
+unsigned long ulMemBase
+struct device *pdev
+unsigned long ulBDMemBase[SWCHANNELNUM]
+unsigned long ulBDMemBasePhy[SWCHANNELNUM]
+unsigned int ulCurrBdReadPtr[SWCHANNELNUM]
+unsigned int ulCurrBdWritePtr[SWCHANNELNUM]
+PSECallBackfn pcallback[SWCHANNELNUM][SWBUFNUM]
+struct completion *stsemphore[SWCHANNELNUM][SWBUFNUM]
+int iIrq
+rwlock_t mr_lock
+struct semaphore sema
}
class tagSEBasicBD {
+unsigned int ucOpCode
+unsigned int ucFlag
+unsigned int ucRetCode
+unsigned int usInputLength
+unsigned int usOutputLength
+unsigned int ulInputLPtr
+unsigned int ulInputHPtr
+unsigned int ulOutputLPtr
+unsigned int ulOutputHPtr
}
tagSEdrvctl "1" o-- "many" tagSEBasicBD : "Manages BDs at ulBDMemBase"
class tag_dma_buf_ctl {
+struct list_head list
+unsigned char *pDmaBuf
}
class tag_Queue_container {
+struct list_head m_Head
+unsigned int qlen
+unsigned int max_qlen
}
tag_Queue_container o-- "0..*" tag_dma_buf_ctl : "Manages DMA Buffers (g_DmaBQueueContainer)"
tag_Queue_container o-- "0..*" ST_SEND_PACKAGE : "Manages Send Queue (g_SendQueueContainer)"
tag_Queue_container o-- "0..*" ST_INT_MESSAGE : "Manages Receive Queue (g_RecQueueContainer)"
class ST_SEND_PACKAGE {
+struct list_head list
+struct tagSEdrvctl *pdrvctl
+unsigned char *pInPtr
+unsigned short usInlen
+PSECallBackfn pcallback
+struct completion *mycomplete
}
ST_SEND_PACKAGE ..> tagSEdrvctl : uses
class ST_INT_MESSAGE {
+struct list_head list
+PSECallBackfn pcallback
+void *pParma
}
class platform_driver {
<<loongson_cryp_driver>>
+loongson_cryp_probe(pdev) int
+loongson_cryp_remove(pdev) int
+se_chip_load() int
+se_chip_unload() void
}
platform_driver ..> tagSEdrvctl : creates/manages (g_psechipDrvCtrl)
class file_operations {
<<SE_fops>>
+se_userwrite()
+se_useropen()
+se_userrelease()
}
file_operations ..> tagSEdrvctl : uses (via g_psechipDrvCtrl)
file_operations ..> ST_SEND_PACKAGE : creates and queues via se_hardtrans
Class Diagram: LoongArch SMP/Topology AdditionsclassDiagram
direction LR
class LoongArch_SMP_Kernel {
+cpumask_t cpu_llc_shared_map[NR_CPUS]
+cpumask_t cpu_sibling_map[NR_CPUS]
+cpumask_t cpu_core_map[NR_CPUS]
+static cpumask_t cpu_llc_shared_setup_map
+set_cpu_llc_shared_map(int cpu) void
+clear_cpu_llc_shared_map(int cpu) void
+smp_prepare_cpus(unsigned int max_cpus) void
+start_secondary(void) void
+loongson_cpu_disable(void) int
}
class LoongArch_Topology_Header {
<<include/asm/topology.h>>
+cpu_coregroup_mask(int cpu) const struct cpumask*
}
LoongArch_Topology_Header ..> LoongArch_SMP_Kernel : "accesses cpu_llc_shared_map"
Class Diagram: Loongson ACPI GPIO Configuration UpdateclassDiagram
class loongson_gpio_chip_data {
+const char *label
+loongson_gpio_ctrl_mode mode
+u32 conf_offset
+u32 in_offset
+u32 out_offset
}
class loongson_gpio_ls7a2000_data1 {
<<constant instance of loongson_gpio_chip_data>>
+label = "ls7a2000_gpio"
+mode = BIT_CTRL_MODE (changed from BYTE_CTRL_MODE)
+conf_offset = 0x4 (changed from 0x84)
+in_offset = 0x8 (changed from 0x88)
+out_offset = 0x0 (changed from 0x80)
}
loongson_gpio_ls7a2000_data1 --|> loongson_gpio_chip_data
File-Level Changes
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Hi @AaronDot. Thanks for your PR. I'm waiting for a deepin-community member to verify that this patch is reasonable to test. If it is, they should reply with Once the patch is verified, the new status will be reflected by the I understand the commands that are listed here. Instructions for interacting with me using PR comments are available here. If you have questions or suggestions related to my behavior, please file an issue against the kubernetes/test-infra repository. |
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Hey @AaronDot - I've reviewed your changes - here's some feedback:
- The new SE crypto driver is extremely large and monolithic—consider splitting it into smaller patches (e.g., core setup, buffer management, IRQ handling) and reusing existing kernel crypto framework helpers to improve maintainability and reviewability.
- The LoongArch-specific IH fix work in amdgpu_ih_ring_init and fini is duplicated; extract common init/teardown functions to avoid code duplication and reduce the chance of inconsistencies.
Here's what I looked at during the review
- 🟡 General issues: 3 issues found
- 🟢 Security: all looks good
- 🟢 Testing: all looks good
- 🟢 Complexity: all looks good
- 🟢 Documentation: all looks good
Help me be more useful! Please click 👍 or 👎 on each comment and I'll use the feedback to improve your reviews.
| return 0; | ||
| } | ||
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| static int loongson_cryp_resume(struct platform_device *pdev) |
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issue (bug_risk): Global state reinitialization in resume may not be thread-safe.
The resume function resets global variables without synchronization, which may cause inconsistent state if accessed by multiple threads. Use locking or refactor to minimize global state.
| } | ||
| return -1; | ||
| } | ||
| static int loongson_cryp_probe(struct platform_device *pdev) |
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suggestion: IRQ assignment logic may not be robust for all resource layouts.
The current approach relies on resource order, which may change. Using platform_get_irq_byname would make IRQ assignment more reliable.
Suggested implementation:
{
int irq;
irq = platform_get_irq_byname(pdev, pat);
if (irq < 0)
return -1;
return irq;
}- Ensure that the device tree or platform data provides named IRQ resources matching the
patargument. - If the rest of the code expects a resource start address rather than an IRQ number, further adaptation may be needed.
| return IRQ_HANDLED; | ||
| } | ||
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| static int se_useropen(struct inode *inode, struct file *file) |
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suggestion (bug_risk): Device open does not implement reference counting or exclusive access.
Concurrent opens are not managed, which may cause issues. Please add reference counting or exclusive access as appropriate for your device.
Suggested implementation:
/* Device private structure for open/exclusive access */
struct se_device_priv {
struct mutex lock;
int is_open;
/* ... other members ... */
};
/* Assume you have a way to get device private data from inode or file.
* For example, using container_of or file->private_data.
* Here, we use a placeholder function: get_se_device_priv()
*/
static int se_useropen(struct inode *inode, struct file *file)
{
struct se_device_priv *priv;
if (MINOR(inode->i_rdev) != 0)
return -ENODEV;
priv = get_se_device_priv(inode, file);
if (!priv)
return -ENODEV;
mutex_lock(&priv->lock);
if (priv->is_open) {
mutex_unlock(&priv->lock);
return -EBUSY; /* Device is already open */
}
priv->is_open = 1;
mutex_unlock(&priv->lock);
/* Optionally, store priv in file->private_data for use in release */
file->private_data = priv;
return SE_OK;
}
/* Add the corresponding release function */
static int se_userrelease(struct inode *inode, struct file *file)
{
struct se_device_priv *priv = file->private_data;
if (!priv)
return -ENODEV;
mutex_lock(&priv->lock);
priv->is_open = 0;
mutex_unlock(&priv->lock);
return 0;
}- You must define and initialize
struct se_device_privfor each device instance, and ensure thelockis initialized (e.g.,mutex_init(&priv->lock)). - Implement the
get_se_device_priv(inode, file)function to retrieve the device's private data. - Register
se_userreleaseas the.releasecallback in yourfile_operationsstructure. - If you want reference counting (multiple opens), replace the
is_openflag with an integer open count and adjust logic accordingly.
| } | ||
| EXPORT_SYMBOL(se_kernelwrite); | ||
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| static long se_userioctl(struct file *filp, u_int cmd, u_long arg) |
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🚨 issue (security): User ioctl handler does not validate cmd or arg.
Currently, the handler ignores cmd and arg, which may confuse userspace and introduce security risks. Please validate or restrict accepted ioctl commands.
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syccess -> success |
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Pull Request Overview
This PR introduces LoongArch platform support with several patches addressing hardware fixes, new driver additions, and extended CPU/core configuration support. Key changes include a fix for the ls7a2000 GPIO crash by updating control modes and register offsets, additions of new crypto and PWM drivers, and multi-core scheduling support with increased NR_CPUS and last-level cache mapping.
Reviewed Changes
Copilot reviewed 34 out of 34 changed files in this pull request and generated no comments.
Show a summary per file
| File | Description |
|---|---|
| drivers/gpio/gpio-loongson-64bit.c | Update GPIO control mode and register offsets to fix kernel crash |
| drivers/crypto/sedriver/wst_se_echip_driver.h | Introduce new crypto chip driver definitions with minor naming issues |
| drivers/crypto/sedriver/wst_se_ktrans.h | New header defining crypto transaction data structures |
| drivers/crypto/sedriver/wst_se_define.h | New driver definitions |
| drivers/crypto/sedriver/wst_se_common_type.h | New common type definitions for the driver |
| drivers/crypto/sedriver/Makefile and Kconfig | Driver build integration and configuration updates |
| arch/loongarch/kernel/smp.c | Add support for last-level cache mapping for multi-core systems |
| arch/loongarch/kernel/acpi.c | Remove redundant helper and enhance error checks |
| arch/loongarch/include/asm/* and arch/loongarch/Kconfig | Update CPU topology, core ID width, and increase NR_CPUS capacity |
| arch/loongarch/configs/* and MAINTAINERS, YAML bindings | Config and documentation updates for new drivers and platform support |
Comments suppressed due to low confidence (4)
drivers/crypto/sedriver/wst_se_echip_driver.h:68
- The field name 'pParma' appears to be a misspelling; consider renaming it to 'pParam' for consistency with the callback parameter naming.
void *pParma[SWCHANNELNUM][SWBUFNUM];
drivers/crypto/sedriver/wst_se_echip_driver.h:158
- The member 'pParma' in the ST_SEND_PACKAGE structure should likely be renamed to 'pParam' to match standard naming conventions and maintain consistency.
void *pParma;
arch/loongarch/Kconfig:465
- The default value for NR_CPUS has been increased to 2048; please ensure that this change is well-documented and validated against hardware capabilities to avoid potential performance or resource allocation issues on systems that do not require such a high CPU count.
default "2048"
drivers/gpio/gpio-loongson-64bit.c:337
- The update from BYTE_CTRL_MODE to BIT_CTRL_MODE and the adjustment of register offsets is significant; please verify that these new values are fully aligned with the ls7a2000 hardware specifications to prevent regressions.
.mode = BIT_CTRL_MODE,
drivers/crypto/sedriver/Kconfig
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| # | ||
| config SW_SE_CHIP | ||
| tristate "wst se chip driver" | ||
| depends on LOONGARCH |
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3A4000也使用的同款处理器，请添加该驱动对MIPS架构的支持（MACH_LOONGSON64）
| @@ -5511,6 +5510,7 @@ CONFIG_PWM_CLK=m | |||
| CONFIG_PWM_DWC=m | |||
| CONFIG_PWM_FSL_FTM=m | |||
| CONFIG_PWM_IQS620A=m | |||
| CONFIG_PWM_LOONGSON=y | |||
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没有特别的原因，看你们的需求，模块形式也是可以的
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没有特别的原因，看你们的需求，模块形式也是可以的
那改成m吧，谢啦
| @@ -1279,6 +1279,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, | |||
| uint64_t seq; | |||
| int r; | |||
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| #ifdef CONFIG_LOONGARCH | |||
| while (amdgpu_ih_fix_is_busy(p->adev)) | |||
| msleep(20); | |||
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为了代码可读性，请在此处添加注释说明原因
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对 AMD 显卡复位问题的规避的补丁，暂时不提交，我会先去掉。
| * FIXME: Disable this workaround until we find a better fix (possibly in | ||
| * the platform-specific PCI code). | ||
| */ | ||
| #ifndef CONFIG_MACH_LOONGSON64 |
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此处修改会不会导致MIPS架构使用AMDGPU出现异常？上下同，请明确这些问题是否7A1000桥片涉及，若涉及，请一律修改架构宏以包含对MIPS的workaround。
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对 AMD 显卡复位问题的规避的补丁，暂时不提交，我会先去掉。
|
Backport自上游的提交，请一律标注上游主线的commit hash，其格式参考linux-stable即可。 |
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如先前沟通，请修改目录和ko名字，sedriver和sw_se_echip_drv.ko的命名让人看不出来这个驱动是给谁用的 |
drivers/crypto/sedriver/Kconfig
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| If you have a wst security chip, | ||
| say Yes and it will be accessible from within Linux. | ||
| To compile this driver as a module, choose M here; | ||
| the module will be called tpm_tis_i2c. If unsure, say N. |
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为什么 the module will be called tpm_tis_i2c.
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复制粘贴的错误，这句话下个版本我会删掉！
目录名：sedriver -> westone 你看这几个名字如何？ |
同意 |
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Fixed kernel crash caused by incorrect Loongson-7A2000 ACPI GPIO chip_data description. According to the register definition, its access mode can only be BIT_CTRL_MODE. Secondly, the register offset needs to match the register base address in the firmware, otherwise the GPIO cannot be accessed normally. Fixes: aac06cf ("LoongArch: Fix i2c related issues") Signed-off-by: Binbin Zhou <[email protected]>
Add support for WST se chip support for LS*5000*. Signed-off-by: Qunqin Zhao <[email protected]> Signed-off-by: Hongchen Zhang <[email protected]> Signed-off-by: Binbin Zhou <[email protected]>
commit 90cd430f04d0f2874f9c0fc75b9084f5162299c9 upstream. Add Loongson PWM controller binding with DT schema format using json-schema. Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Huacai Chen <[email protected]> Signed-off-by: Binbin Zhou <[email protected]> Link: https://lore.kernel.org/r/57e0cbd4b7ce37da94094205e28a2ec2256c7175.1743403075.git.zhoubinbin@loongson.cn Signed-off-by: Uwe Kleine-König <[email protected]>
commit 2b62c89448dd41ebf16d860c52fe9a8aba3dd8a3 upstream. This commit adds a generic PWM framework driver for the PWM controller found on Loongson family chips. [Some APIs have been modified to adapt to v6.6 and add pwm_loongson to config file.] Acked-by: Huacai Chen <[email protected]> Co-developed-by: Juxin Gao <[email protected]> Signed-off-by: Juxin Gao <[email protected]> Signed-off-by: Binbin Zhou <[email protected]> Link: https://lore.kernel.org/r/76050a903a8015422fb9261ad88c7d9cc2edbbd8.1743403075.git.zhoubinbin@loongson.cn Signed-off-by: Uwe Kleine-König <[email protected]>
commit dcb882bd436e2124e37640671cfa773dfaed485c upstream. mul_u64_u64_div_u64() returns an u64 that might be bigger than U32_MAX. To properly handle this case it must not be directly assigned to an u32 value. Use a wider type for duty and period to make the idiom: duty = mul_u64_u64_div_u64(...) if (duty > U32_MAX) duty = U32_MAX; actually work as intended. Reported-by: Dan Carpenter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: 2b62c89448dd ("pwm: Add Loongson PWM controller support") Signed-off-by: Uwe Kleine-König <[email protected]> Reviewed-by: Binbin Zhou <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Binbin Zhou <[email protected]>
commit 9559d5806319a9254d9053b22a31324e1929aac6 upstream.
Increase max supported CPUs up to 2048, including:
1. Increase CSR.CPUID register's effective width;
2. Define MAX_CORE_PIC (a.k.a. max physical ID) to 2048;
3. Allow NR_CPUS (a.k.a. max logical ID) to be as large as 2048;
4. Introduce acpi_numa_x2apic_affinity_init() to handle ACPI SRAT
for CPUID >= 256.
Note: The reason of increasing to 2048 rather than 4096/8192 is because
the IPI hardware can only support 2048 as a maximum.
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Binbin Zhou <[email protected]>
commit 93f437315660219245f99724d7597e5b2ea40df3 upstream. In order to achieve more reasonable load balancing behavior, add SCHED_MC (Multi-core scheduler) support. The LLC distribution of LoongArch now is consistent with NUMA node, the balancing domain of SCHED_MC can effectively reduce the situation where processes are awakened to smt_sibling. Co-developed-by: Hongliang Wang <[email protected]> Signed-off-by: Hongliang Wang <[email protected]> Signed-off-by: Tianyang Zhang <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Hongchen Zhang <[email protected]> Signed-off-by: Binbin Zhou <[email protected]>
commit f438eee2c8c93320d70cdee7630a06baaa47a304 upstream. Currently, the tx and rx queue number initialization is duplicated in loongson_gmac_data() and loongson_gnet_data(), so move it to the common function loongson_default_data(). This is a preparation for later patches. Reviewed-by: Yanteng Si <[email protected]> Tested-by: Henry Chen <[email protected]> Tested-by: Biao Dong <[email protected]> Signed-off-by: Baoqi Zhang <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: David S. Miller <[email protected]> Signed-off-by: Binbin Zhou <[email protected]>
commit 2725fc2e0b6113ea9e655b77409d6129876e45e9 upstream. Add a new multi-chan IP core (0x12) support which is used in Loongson- 2K3000/Loongson-3B6000M. Compared with the 0x10 core, the new 0x12 core reduces channel numbers from 8 to 4, but checksum is supported for all channels. Add a "multichan" flag to loongson_data, so that we can simply use a "if (ld->multichan)" condition rather than the complicated condition "if (ld->loongson_id == DWMAC_CORE_MULTICHAN_V1 || ld->loongson_id == DWMAC_CORE_MULTICHAN_V2)". Reviewed-by: Andrew Lunn <[email protected]> Tested-by: Henry Chen <[email protected]> Tested-by: Biao Dong <[email protected]> Signed-off-by: Baoqi Zhang <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Reviewed-by: Yanteng Si <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]> Signed-off-by: Binbin Zhou <[email protected]>
commit ef1179f78119c243bdc276cfb819242bc35308cd upstream. Add a new GMAC's PCI device ID (0x7a23) support which is used in Loongson-2K3000/Loongson-3B6000M. The new GMAC device use external PHY, so it reuses loongson_gmac_data() as the old GMAC device (0x7a03), and the new GMAC device still doesn't support flow control now. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Yanteng Si <[email protected]> Tested-by: Henry Chen <[email protected]> Tested-by: Biao Dong <[email protected]> Signed-off-by: Baoqi Zhang <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]> Signed-off-by: Binbin Zhou <[email protected]>
support intel i225/i226 network card driver. Signed-off-by: wanghongliang <[email protected]> Signed-off-by: Hongchen Zhang <[email protected]> Signed-off-by: Binbin Zhou <[email protected]>
Enable gpio-pca953x driver. Signed-off-by: wanghongliang <[email protected]> Signed-off-by: Hongchen Zhang <[email protected]> Signed-off-by: Binbin Zhou <[email protected]>
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[APPROVALNOTIFIER] This PR is NOT APPROVED This pull-request has been approved by: The full list of commands accepted by this bot can be found here.
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Avenger-285714
merged commit 3ae3bce
into
deepin-community:linux-6.6.y
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@AaronDot Hi， Although this PR has been merged, I need to leave a public note here. In principle, Loongson has an obligation to ensure the WST driver compiles on MIPS architecture and to provide user-space test cases for it. If Loongson fails to provide support for MIPS processors like the 3A4000 for the 6.6 kernel, an official statement from them is required. As one of the kernel maintainers for the deepin community, I understand this is difficult for you and your colleagues, and the current lack of MIPS adaptation isn't your personal fault. However, Loongson as a company hasn't fully met its responsibilities. One day in the future, this driver should implement its support for 3A4000 processors and its code style and quality should adhere as closely as possible to upstream standards. |
Disclaimer: Please note that the statements above represent solely the perspective of the code open-source community. |
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Introduction to the patchset:
Patch 1: Fixed kernel crash caused by incorrect parameters in Loongson-7A2000 ACPI GPIO driver.
Patch 2-7: After communicating with Bai Mingcong, it's the more complete workaround for cache flush problems in radeon and amdgpu. However, we need to do more thorough testing.
Patch 8: Add wst crypto se driver
Patch 9-11: Add Loongson PWM driver from upstream
Patch 12: LoongArch 2048 cores support
Patch 13: LoongArch SCHED_MC support
Patch 14-15: More config enabled
Patch 16-18: Loongson-2K3000 GMAC support
Summary by Sourcery
Introduce new Loongson platform support by adding a hardware crypto engine driver, PWM controller driver, and multi-channel GMAC support; extend LoongArch architecture for up to 2048 cores, multi-core scheduling with cache topology, and ACPI affinity; fix GPIO and GPU cache ordering bugs; and enable relevant configs and build integrations.
New Features:
Bug Fixes:
Enhancements:
Build:
Documentation: