Skip to content

handle large stack frame prolog/epilog #21506

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 5, 2025
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 19 additions & 1 deletion compiler/src/dmd/backend/arm/cod3.d
Original file line number Diff line number Diff line change
Expand Up @@ -788,7 +788,25 @@
else
{
if (log) printf("epilog: mov sp,bp\n");
cdbx.gen1(INSTR.ldstpair_post(2, 0, 1, cast(uint)(16 + localsize) / 8, 30, 31, 29)); // LDP x29,x30,[sp],#16 + localsize
if (16 + xlocalsize <= 512) // or localsize??
cdbx.gen1(INSTR.ldstpair_post(2, 0, 1, cast(uint)(16 + localsize) / 8, 30, 31, 29)); // LDP x29,x30,[sp],#16 + localsize

Check warning on line 792 in compiler/src/dmd/backend/arm/cod3.d

View check run for this annotation

Codecov / codecov/patch

compiler/src/dmd/backend/arm/cod3.d#L791-L792

Added lines #L791 - L792 were not covered by tests
else
{
/* LDP x29,x30,[sp] https://www.scs.stanford.edu/~zyedidia/arm64/ldp_gen.html
*/
uint opc = 2;
uint VR = 0;
uint L = 1;
uint imm7 = 0;
reg_t Rt2 = 30;
reg_t Rn = 0x1F;
reg_t Rt = 29;
cdbx.gen1(INSTR.ldstpair_off(opc,VR,L,imm7,Rt2,Rn,Rt));

Check warning on line 804 in compiler/src/dmd/backend/arm/cod3.d

View check run for this annotation

Codecov / codecov/patch

compiler/src/dmd/backend/arm/cod3.d#L797-L804

Added lines #L797 - L804 were not covered by tests
/* ADD sp,sp,#off
* ADD sp,sp,#off + lsl #12
*/
cod3_stackadj(cdbx, cast(int)(-(16 + xlocalsize)));

Check warning on line 808 in compiler/src/dmd/backend/arm/cod3.d

View check run for this annotation

Codecov / codecov/patch

compiler/src/dmd/backend/arm/cod3.d#L808

Added line #L808 was not covered by tests
}
}
}
else
Expand Down
22 changes: 9 additions & 13 deletions compiler/src/dmd/backend/x86/cod3.d
Original file line number Diff line number Diff line change
Expand Up @@ -3591,24 +3591,21 @@
else
{
/* SUB sp,sp,#16+xlocalsize
STP x29,x30,[sp]
*/
cod3_stackadj(cdb, 16 + xlocalsize);

assert((xlocalsize & 0xF) == 0); // 16 byte aligned

// https://www.scs.stanford.edu/~zyedidia/arm64/stp_gen.html
// STP x29,x30,[sp,#xlocalsize]
// STP x29,x30,[sp]
{
uint opc = 2;
uint VR = 0;
uint L = 0;
uint imm7 = xlocalsize >> 3;
assert(imm7 < (1 << 7)); // only 7 bits allowed
imm7 = 0;
ubyte Rt2 = 30;
ubyte Rn = 0x1F;
ubyte Rt = 29;
uint imm7 = 0;
reg_t Rt2 = 30;
reg_t Rn = 0x1F;
reg_t Rt = 29;

Check warning on line 3608 in compiler/src/dmd/backend/x86/cod3.d

View check run for this annotation

Codecov / codecov/patch

compiler/src/dmd/backend/x86/cod3.d#L3605-L3608

Added lines #L3605 - L3608 were not covered by tests
cdb.gen1(INSTR.ldstpair_off(opc, VR, L, imm7, Rt2, Rn, Rt));
}
}
Expand All @@ -3620,11 +3617,10 @@
uint op = 0;
uint S = 0;
uint sh = 0;
uint imm12 = 0; //xlocalsize;
assert(imm12 < (1 << 12)); // only 12 bits allowed
ubyte Rn = 0x1F;
ubyte Rd = 29;
cdb.gen1(INSTR.addsub_imm(sf, op, S, sh, imm12, Rn, Rd)); // mov x29,sp // x29 points to previous x29
uint imm12 = 0;
reg_t Rn = 0x1F;
reg_t Rd = 29;
cdb.gen1(INSTR.addsub_imm(sf, op, S, sh, imm12, Rn, Rd)); // MOV x29,sp // x29 points to previous x29

Check warning on line 3623 in compiler/src/dmd/backend/x86/cod3.d

View check run for this annotation

Codecov / codecov/patch

compiler/src/dmd/backend/x86/cod3.d#L3620-L3623

Added lines #L3620 - L3623 were not covered by tests
}
}
else
Expand Down
Loading