Skip to content
View eightycc's full-sized avatar

Block or report eightycc

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Open-source Windows and Office activator featuring HWID, Ohook, TSforge, KMS38, and Online KMS activation methods, along with advanced troubleshooting.

Batchfile 135,249 13,141 Updated May 18, 2025

Tiny loaders for various binary formats.

C 237 44 Updated May 4, 2016

TIC-80 is a fantasy computer for making, playing and sharing tiny games.

C 5,359 523 Updated May 10, 2025

Python package of Burrows-Wheeler Transform and its variants.

Python 3 Updated Aug 1, 2019

CircuitPython Webserver, optimized for embedded use

Python 1 Updated Oct 22, 2024

Capture your oscilliscope screen in a .png file

Python 16 4 Updated Nov 16, 2024

A Nextcloud setup exclusively for local networks.

Shell 13 3 Updated Feb 12, 2023
Python 83 12 Updated Jan 24, 2025

A Kmk firmware flashing and configuration tool

Vue 440 34 Updated Feb 8, 2025

Updated version of joedevivo/vscode-circuitpython

TypeScript 29 3 Updated Feb 9, 2025

A curated list of awesome CircuitPython guides, videos, libraries, frameworks, software and resources.

676 69 Updated Apr 22, 2025

Some CircuitPython tricks, mostly reminders to myself

Python 692 74 Updated May 7, 2025

5-stage RISC-V CPU, originally developed for RISCBoy

Verilog 27 1 Updated Jul 1, 2023

3-stage RV32IMACZb* processor with debug

Verilog 854 63 Updated May 7, 2025

A toy prime number generator in Verilog

Verilog 10 1 Updated Oct 9, 2016

A simple verilog example for returning the index of the first '1' for data with length of N

SystemVerilog 2 Updated Jun 30, 2021

Yosys Open SYnthesis Suite

C++ 3,815 942 Updated May 17, 2025

SystemVerilog to Verilog conversion

Haskell 628 59 Updated May 18, 2025
SystemVerilog 71 10 Updated Aug 6, 2024

Web-based emulator and operating environment for the Bendix G-15 computer system.

JavaScript 28 5 Updated May 11, 2025

Common source and object code repository for emulators of the Bendix G-15 computer system.

HTML 5 Updated May 11, 2025

SPI Slave for FPGA in Verilog and VHDL

Verilog 199 71 Updated May 11, 2024

Simple command-line program to test HIDAPI

C 295 34 Updated May 20, 2024

Historical versions of Reinhold P. Weicker's Dhrystone benchmark

C 136 76 Updated May 20, 2012

Icarus Verilog

C++ 3,043 550 Updated May 12, 2025