🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VRoom! RISC-V CPU

My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA

SHA3-256 is an encryption algorithm. The project is designed using System Verilog and synthesised using Synopsys DC

My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu

Must-have verilog systemverilog modules

BaseJump STL: A Standard Template Library for SystemVerilog

Naive Educational RISC-V -- A simple single-stage RV32I processor

RISC-V Formal Verification Framework

A List of Free and Open Source Hardware Verification Tools and Frameworks