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riscv-vector-tests Public
Forked from chipsalliance/riscv-vector-testsThe missing test suite for RISC-V V extension.
Go MIT License UpdatedMay 12, 2025 -
analyze-spec-benchmarks Public
Forked from preshing/analyze-spec-benchmarksPython UpdatedApr 29, 2025 -
llvm-project Public
Forked from llvm/llvm-projectThe LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
LLVM Other UpdatedApr 16, 2025 -
chisel3 Public
Forked from chipsalliance/chiselChisel 3: A Modern Hardware Design Language
Scala UpdatedFeb 13, 2025 -
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riscv-isa-manual Public
Forked from riscv/riscv-isa-manualRISC-V Instruction Set Manual
TeX Creative Commons Attribution 4.0 International UpdatedJul 31, 2024 -
coremark-pro Public
Forked from eembc/coremark-proContaining dozens of real-world and synthetic tests, CoreMark®-PRO (2015) is an industry-standard benchmark that measures the multi-processor performance of central processing units (CPU) and embed…
C Other UpdatedJul 18, 2024 -
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riscv-OpenBLAS Public
Forked from OpenMathLib/OpenBLASOpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.
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embench-iot Public
Forked from embench/embench-iotThe main Embench repository
C GNU General Public License v3.0 UpdatedMay 18, 2023 -
DRAMSim2 Public
Forked from firesim/DRAMSim2DRAMSim2: A cycle accurate DRAM simulator
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fa22tapeout-course-dev Public
Forked from jzhou1318/fa22tapeout-course-devHTML BSD 3-Clause "New" or "Revised" License UpdatedJan 5, 2023 -
riscv-isa-sim Public
Forked from riscv-software-src/riscv-isa-simSpike, a RISC-V ISA Simulator
C Other UpdatedDec 12, 2022 -
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rocket-chip Public
Forked from chipsalliance/rocket-chipRocket Chip Generator
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block-inclusivecache-sifive Public
Forked from sifive/block-inclusivecache-sifiveScala Apache License 2.0 UpdatedFeb 6, 2021 -
Git Source Code Mirror - This is a publish-only repository and all pull requests are ignored. Please follow Documentation/SubmittingPatches procedure for any of your improvements.
C Other UpdatedDec 23, 2020 -
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The…
C++ BSD 3-Clause "New" or "Revised" License UpdatedDec 17, 2020 -
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ariane Public
Forked from openhwgroup/cva6Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedMay 31, 2020 -
riscv-gnu-toolchain Public
Forked from riscv-collab/riscv-gnu-toolchainGNU toolchain for RISC-V, including GCC
C Other UpdatedMar 5, 2020 -
firrtl Public
Forked from chipsalliance/firrtlFlexible Intermediate Representation for RTL
Scala UpdatedFeb 12, 2020 -
sifive-blocks Public
Forked from sifive/sifive-blocksCommon RTL blocks used in SiFive's projects
Scala Apache License 2.0 UpdatedDec 2, 2019 -
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riscv-pk Public
Forked from riscv-software-src/riscv-pkRISC-V Proxy Kernel
C Other UpdatedOct 2, 2019 -
Open Neural Network Exchange
PureBasic MIT License UpdatedOct 1, 2019