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Python module containing system_verilog files for coreblocks cpu (for use with LiteX).

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pythondata-cpu-coreblocks

Coreblocks cpu packaged for use with LiteX.

gen_verilog is wrapped with PEP723 compatible script gen_verilog_wrapper.py, to be run with pipx with correct python version and environment.

This package is python version independent. If you want to install dependencies to your environment and elaborate with your python, set RUN_NATIVE in pythondata_cpu_coreblocks/__init__.py (read by LiteX), and install [native] optional requirements.

Installing manually

git clone https://github.com/kuznia-rdzeni/pythondata-cpu-coreblocks.git
cd pythondata-cpu-coreblocks
git submodule update --init
pip install .

Manually install coreblocks dependencies:

pip install -r .[native]
# or, if you changed submodule:
pip install -r pythondata_cpu_coreblocks/sources/requirements.txt

Elaborate core to Verilog

pipx run --python 3.11 --fetch-missing-python pythondata_cpu_coreblocks/gen_verilog_wrapper.py <args>

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Python module containing system_verilog files for coreblocks cpu (for use with LiteX).

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