-
Notifications
You must be signed in to change notification settings - Fork 13.5k
[CodeGen] For ad hoc aliasing, additional regUnits are needed to fix lanemask representation #139206
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Closed
vg0204
wants to merge
3
commits into
llvm:main
from
vg0204:vg0204/handling-regunit-for-ad-hoc-aliaising
+275
−12
Closed
[CodeGen] For ad hoc aliasing, additional regUnits are needed to fix lanemask representation #139206
Changes from all commits
Commits
Show all changes
3 commits
Select commit
Hold shift + click to select a range
File filter
Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
There are no files selected for viewing
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,87 @@ | ||
// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK | ||
// Checks that tablegen calculation of register unit's lanemask. | ||
// It covers the scenario, where leaf aliasing registers are used to create | ||
// disjoint subregs for defining new register (this case inspired from VE tablegen) | ||
// | ||
// For each such leaf register, a unique regUnit will be created that should rightfully | ||
// denote its position in the super register via laneMask. whereas, both of will also | ||
// have a common regUnit that accurately represents the ad hoc aliasing, even though its | ||
// laneMask could be arbitrary which is still better situation. | ||
|
||
include "llvm/Target/Target.td" | ||
|
||
class MyReg<string n, list<Register> subregs = [], list<Register> aliases = []> | ||
: Register<n> { | ||
let Namespace = "Test"; | ||
let SubRegs = subregs; | ||
let Aliases = aliases; | ||
let CoveredBySubRegs = 1; | ||
} | ||
class MyClass<int size, list<ValueType> types, dag registers> | ||
: RegisterClass<"Test", types, size, registers> { | ||
let Size = size; | ||
} | ||
|
||
def sub_i32 : SubRegIndex<32, 32>; // High 32 bit (32..63) | ||
def sub_f32 : SubRegIndex<32>; // Low 32 bit (0..31) | ||
|
||
// Registers SW0 & SF0 are aliases | ||
|
||
// VE's Registers Example: | ||
// SX0 -- SW0 (sub_f32) | ||
// \- SF0 (sub_i32) | ||
def SW0 : MyReg<"sw0", []>; | ||
|
||
def SF0 : MyReg<"sf0", [], [!cast<MyReg>("SW0")]>; | ||
|
||
let SubRegIndices = [sub_f32, sub_i32] in { | ||
def SX0 : MyReg<"s0", [!cast<MyReg>("SW0"), !cast<MyReg>("SF0")]>; | ||
} | ||
|
||
def I64 : MyClass<1, [i64], (add (sequence "SX%u", 0, 0))>; | ||
|
||
def TestTarget : Target; | ||
|
||
// CHECK: RegisterClass I64: | ||
// CHECK: LaneMask: 0000000000000003 | ||
// CHECK: HasDisjunctSubRegs: 1 | ||
// CHECK: CoveredBySubRegs: 1 | ||
// CHECK: Regs: SX0 | ||
// CHECK: SubClasses: I64 | ||
// CHECK: SuperClasses: | ||
|
||
// CHECK: SubRegIndex sub_f32: | ||
// CHECK-NEXT: LaneMask: 0000000000000001 | ||
// CHECK: SubRegIndex sub_i32: | ||
// CHECK-NEXT: LaneMask: 0000000000000002 | ||
|
||
// CHECK: Register SF0: | ||
// CHECK: CoveredBySubregs: 1 | ||
// CHECK: HasDisjunctSubRegs: 0 | ||
// CHECK: Native RegUnit: SF0 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF | ||
// CHECK: Native RegUnit: SF0~SW0 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF | ||
|
||
// CHECK: Register SW0: | ||
// CHECK: CoveredBySubregs: 1 | ||
// CHECK: HasDisjunctSubRegs: 0 | ||
// CHECK: Native RegUnit: SF0~SW0 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF | ||
// CHECK: Native RegUnit: SW0 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF | ||
|
||
// CHECK: Register SX0: | ||
// CHECK: HasDisjunctSubRegs: 1 | ||
// CHECK: SubReg sub_f32 = SW0 | ||
// CHECK: RegUnit SW0 : SF0~SW0 | ||
// CHECK: RegUnit SW0 : SW0 | ||
// CHECK: SubReg sub_i32 = SF0 | ||
// CHECK: RegUnit SF0 : SF0 | ||
// CHECK: RegUnit SF0 : SF0~SW0 | ||
// CHECK: Native RegUnit: SF0 | ||
// CHECK: LaneMask Value: 0000000000000002 | ||
// CHECK: Native RegUnit: SF0~SW0 | ||
// CHECK: LaneMask Value: 0000000000000000 | ||
// CHECK: Native RegUnit: SW0 | ||
// CHECK: LaneMask Value: 0000000000000001 |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,132 @@ | ||
// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK | ||
// Checks that tablegen calculation of register unit's lanemask. | ||
// It covers the scenario, where non-leaf aliasing registers are used to create | ||
// disjoint subregs for defining new register (this case inspired from VE tablegen) | ||
// This test is inspired via hypothetical extrapolating VE's registers backend. | ||
// | ||
// This situation is identical to the test DisjoinLeafAliasSubregs.td, except the | ||
// fact, that here the alias registers are not only used as mutually disjoint subregs | ||
// to define new register, but also these alias registers are not necessarily the | ||
// the leaf registers, implying they themselves are made out of subregs. | ||
// | ||
// Here also, the lanemask corresponding to unique regUnit will be accurately tell | ||
// regUnit position, whereas the laneMask for common regunit, accounting for aliasing | ||
// , could be still arbitrary based on the exact super register its part of. | ||
|
||
include "llvm/Target/Target.td" | ||
|
||
class MyReg<string n, list<Register> subregs = [], list<Register> aliases = []> | ||
: Register<n> { | ||
let Namespace = "Test"; | ||
let SubRegs = subregs; | ||
let Aliases = aliases; | ||
let CoveredBySubRegs = 1; | ||
} | ||
class MyClass<int size, list<ValueType> types, dag registers> | ||
: RegisterClass<"Test", types, size, registers> { | ||
let Size = size; | ||
} | ||
|
||
def sub_i16 : SubRegIndex<16, 16>; // High 16 bit (16..31) | ||
def sub_f16 : SubRegIndex<16>; // Low 16 bit (0..15) | ||
def sub_i32 : SubRegIndex<32, 32>; // High 32 bit (32..63) | ||
def sub_f32 : SubRegIndex<32>; // Low 32 bit (0..31) | ||
|
||
// Registers SW0 & SF0 are aliases | ||
|
||
// VE's Registers Extrapolated example: | ||
// SX0 -- SW0 (sub_f32) -- SW0_LO16 (sub_f16) | ||
// \ \- SW0_HI16 (sub_i16) | ||
// \- SF0 (sub_i32) | ||
def SW0_LO16 : MyReg<"sw0_lo16", []>; | ||
def SW0_HI16 : MyReg<"sw0_hi16", []>; | ||
|
||
let SubRegIndices = [sub_f16, sub_i16] in { | ||
def SW0 : MyReg<"sw1", [SW0_LO16, SW0_HI16]>; | ||
} | ||
|
||
def SF0 : MyReg<"sf0", [], [!cast<MyReg>("SW0")]>; | ||
|
||
let SubRegIndices = [sub_f32, sub_i32] in { | ||
def SX0 : MyReg<"s0", [!cast<MyReg>("SW0"), !cast<MyReg>("SF0")]>; | ||
} | ||
|
||
def I64 : MyClass<1, [i64], (add (sequence "SX%u", 0, 0))>; | ||
|
||
def TestTarget : Target; | ||
|
||
// CHECK: RegisterClass I64: | ||
// CHECK: LaneMask: 0000000000000007 | ||
// CHECK: HasDisjunctSubRegs: 1 | ||
// CHECK: CoveredBySubRegs: 1 | ||
// CHECK: Regs: SX0 | ||
// CHECK: SubClasses: I64 | ||
// CHECK: SuperClasses: | ||
|
||
// CHECK: SubRegIndex sub_f16: | ||
// CHECK-NEXT: LaneMask: 0000000000000001 | ||
// CHECK: SubRegIndex sub_f32: | ||
// CHECK-NEXT: LaneMask: 0000000000000003 | ||
// CHECK: SubRegIndex sub_i16: | ||
// CHECK-NEXT: LaneMask: 0000000000000002 | ||
// CHECK: SubRegIndex sub_i32: | ||
// CHECK-NEXT: LaneMask: 0000000000000004 | ||
|
||
// CHECK: Register SF0: | ||
// CHECK: CoveredBySubregs: 1 | ||
// CHECK: HasDisjunctSubRegs: 0 | ||
// CHECK: Native RegUnit: SF0 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF | ||
// CHECK: Native RegUnit: SF0~SW0 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF | ||
|
||
// CHECK: Register SW0: | ||
// CHECK: CoveredBySubregs: 1 | ||
// CHECK: HasDisjunctSubRegs: 1 | ||
// CHECK: SubReg sub_f16 = SW0_LO16 | ||
// CHECK: RegUnit SW0_LO16 : SW0_LO16 | ||
// CHECK: SubReg sub_i16 = SW0_HI16 | ||
// CHECK: RegUnit SW0_HI16 : SW0_HI16 | ||
// CHECK: Native RegUnit: SF0~SW0 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF | ||
// CHECK: Native RegUnit: SW0_LO16 | ||
// CHECK: LaneMask Value: 0000000000000001 | ||
// CHECK: Native RegUnit: SW0_HI16 | ||
// CHECK: LaneMask Value: 0000000000000002 | ||
|
||
// CHECK: Register SX0: | ||
// CHECK: CoveredBySubregs: 1 | ||
// CHECK: HasDisjunctSubRegs: 1 | ||
// CHECK: SubReg sub_f16 = SW0_LO16 | ||
// CHECK: RegUnit SW0_LO16 : SW0_LO16 | ||
// CHECK: SubReg sub_f32 = SW0 | ||
// CHECK: RegUnit SW0 : SF0~SW0 | ||
// CHECK: RegUnit SW0 : SW0_LO16 | ||
// CHECK: RegUnit SW0 : SW0_HI16 | ||
// CHECK: SubReg sub_i16 = SW0_HI16 | ||
// CHECK: RegUnit SW0_HI16 : SW0_HI16 | ||
// CHECK: SubReg sub_i32 = SF0 | ||
// CHECK: RegUnit SF0 : SF0 | ||
// CHECK: RegUnit SF0 : SF0~SW0 | ||
// CHECK: Native RegUnit: SF0 | ||
// CHECK: LaneMask Value: 0000000000000004 | ||
// CHECK: Native RegUnit: SF0~SW0 | ||
// CHECK: LaneMask Value: 0000000000000004 | ||
// CHECK: Native RegUnit: SW0_LO16 | ||
// CHECK: LaneMask Value: 0000000000000001 | ||
// CHECK: Native RegUnit: SW0_HI16 | ||
// CHECK: LaneMask Value: 0000000000000002 | ||
|
||
// CHECK: Register SW0_HI16: | ||
// CHECK: CostPerUse: 0 | ||
// CHECK: CoveredBySubregs: 1 | ||
// CHECK: HasDisjunctSubRegs: 0 | ||
// CHECK: Native RegUnit: SW0_HI16 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF | ||
|
||
// CHECK: Register SW0_LO16: | ||
// CHECK: CostPerUse: 0 | ||
// CHECK: CoveredBySubregs: 1 | ||
// CHECK: HasDisjunctSubRegs: 0 | ||
// CHECK: Native RegUnit: SW0_LO16 | ||
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
As an alternative implementation, could you simply move this block before the "Absent any ad hoc aliasing..." block?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Why so? Because the handling of leaf register without ad hoc aliasing is really happening after this from line 456 if you see!
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
The current logic is:
I am suggesting swapping #2 and #3:
I think this gives the desired behavior.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
This won't do as suppose intially once
sw0
got regunit SW0 & SW0-SF0 (after step 2 and 3), at the same time in its step2,sf0
will get its regunit SW0-SF0. So when it comes to registersf0
, its step2 (only if regunit empty) to give its unique regunit SW0.There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I see, but it is pretty easy to fix that problem. See #139526