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[CodeGen] For ad hoc aliasing, additional regUnits are needed to fix lanemask representation #139206

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87 changes: 87 additions & 0 deletions llvm/test/TableGen/DisjointLeafAliasSubregs.td
Original file line number Diff line number Diff line change
@@ -0,0 +1,87 @@
// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK
// Checks that tablegen calculation of register unit's lanemask.
// It covers the scenario, where leaf aliasing registers are used to create
// disjoint subregs for defining new register (this case inspired from VE tablegen)
//
// For each such leaf register, a unique regUnit will be created that should rightfully
// denote its position in the super register via laneMask. whereas, both of will also
// have a common regUnit that accurately represents the ad hoc aliasing, even though its
// laneMask could be arbitrary which is still better situation.

include "llvm/Target/Target.td"

class MyReg<string n, list<Register> subregs = [], list<Register> aliases = []>
: Register<n> {
let Namespace = "Test";
let SubRegs = subregs;
let Aliases = aliases;
let CoveredBySubRegs = 1;
}
class MyClass<int size, list<ValueType> types, dag registers>
: RegisterClass<"Test", types, size, registers> {
let Size = size;
}

def sub_i32 : SubRegIndex<32, 32>; // High 32 bit (32..63)
def sub_f32 : SubRegIndex<32>; // Low 32 bit (0..31)

// Registers SW0 & SF0 are aliases

// VE's Registers Example:
// SX0 -- SW0 (sub_f32)
// \- SF0 (sub_i32)
def SW0 : MyReg<"sw0", []>;

def SF0 : MyReg<"sf0", [], [!cast<MyReg>("SW0")]>;

let SubRegIndices = [sub_f32, sub_i32] in {
def SX0 : MyReg<"s0", [!cast<MyReg>("SW0"), !cast<MyReg>("SF0")]>;
}

def I64 : MyClass<1, [i64], (add (sequence "SX%u", 0, 0))>;

def TestTarget : Target;

// CHECK: RegisterClass I64:
// CHECK: LaneMask: 0000000000000003
// CHECK: HasDisjunctSubRegs: 1
// CHECK: CoveredBySubRegs: 1
// CHECK: Regs: SX0
// CHECK: SubClasses: I64
// CHECK: SuperClasses:

// CHECK: SubRegIndex sub_f32:
// CHECK-NEXT: LaneMask: 0000000000000001
// CHECK: SubRegIndex sub_i32:
// CHECK-NEXT: LaneMask: 0000000000000002

// CHECK: Register SF0:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 0
// CHECK: Native RegUnit: SF0
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF
// CHECK: Native RegUnit: SF0~SW0
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF

// CHECK: Register SW0:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 0
// CHECK: Native RegUnit: SF0~SW0
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF
// CHECK: Native RegUnit: SW0
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF

// CHECK: Register SX0:
// CHECK: HasDisjunctSubRegs: 1
// CHECK: SubReg sub_f32 = SW0
// CHECK: RegUnit SW0 : SF0~SW0
// CHECK: RegUnit SW0 : SW0
// CHECK: SubReg sub_i32 = SF0
// CHECK: RegUnit SF0 : SF0
// CHECK: RegUnit SF0 : SF0~SW0
// CHECK: Native RegUnit: SF0
// CHECK: LaneMask Value: 0000000000000002
// CHECK: Native RegUnit: SF0~SW0
// CHECK: LaneMask Value: 0000000000000000
// CHECK: Native RegUnit: SW0
// CHECK: LaneMask Value: 0000000000000001
132 changes: 132 additions & 0 deletions llvm/test/TableGen/DisjointNonLeafAliasSubregs.td
Original file line number Diff line number Diff line change
@@ -0,0 +1,132 @@
// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK
// Checks that tablegen calculation of register unit's lanemask.
// It covers the scenario, where non-leaf aliasing registers are used to create
// disjoint subregs for defining new register (this case inspired from VE tablegen)
// This test is inspired via hypothetical extrapolating VE's registers backend.
//
// This situation is identical to the test DisjoinLeafAliasSubregs.td, except the
// fact, that here the alias registers are not only used as mutually disjoint subregs
// to define new register, but also these alias registers are not necessarily the
// the leaf registers, implying they themselves are made out of subregs.
//
// Here also, the lanemask corresponding to unique regUnit will be accurately tell
// regUnit position, whereas the laneMask for common regunit, accounting for aliasing
// , could be still arbitrary based on the exact super register its part of.

include "llvm/Target/Target.td"

class MyReg<string n, list<Register> subregs = [], list<Register> aliases = []>
: Register<n> {
let Namespace = "Test";
let SubRegs = subregs;
let Aliases = aliases;
let CoveredBySubRegs = 1;
}
class MyClass<int size, list<ValueType> types, dag registers>
: RegisterClass<"Test", types, size, registers> {
let Size = size;
}

def sub_i16 : SubRegIndex<16, 16>; // High 16 bit (16..31)
def sub_f16 : SubRegIndex<16>; // Low 16 bit (0..15)
def sub_i32 : SubRegIndex<32, 32>; // High 32 bit (32..63)
def sub_f32 : SubRegIndex<32>; // Low 32 bit (0..31)

// Registers SW0 & SF0 are aliases

// VE's Registers Extrapolated example:
// SX0 -- SW0 (sub_f32) -- SW0_LO16 (sub_f16)
// \ \- SW0_HI16 (sub_i16)
// \- SF0 (sub_i32)
def SW0_LO16 : MyReg<"sw0_lo16", []>;
def SW0_HI16 : MyReg<"sw0_hi16", []>;

let SubRegIndices = [sub_f16, sub_i16] in {
def SW0 : MyReg<"sw1", [SW0_LO16, SW0_HI16]>;
}

def SF0 : MyReg<"sf0", [], [!cast<MyReg>("SW0")]>;

let SubRegIndices = [sub_f32, sub_i32] in {
def SX0 : MyReg<"s0", [!cast<MyReg>("SW0"), !cast<MyReg>("SF0")]>;
}

def I64 : MyClass<1, [i64], (add (sequence "SX%u", 0, 0))>;

def TestTarget : Target;

// CHECK: RegisterClass I64:
// CHECK: LaneMask: 0000000000000007
// CHECK: HasDisjunctSubRegs: 1
// CHECK: CoveredBySubRegs: 1
// CHECK: Regs: SX0
// CHECK: SubClasses: I64
// CHECK: SuperClasses:

// CHECK: SubRegIndex sub_f16:
// CHECK-NEXT: LaneMask: 0000000000000001
// CHECK: SubRegIndex sub_f32:
// CHECK-NEXT: LaneMask: 0000000000000003
// CHECK: SubRegIndex sub_i16:
// CHECK-NEXT: LaneMask: 0000000000000002
// CHECK: SubRegIndex sub_i32:
// CHECK-NEXT: LaneMask: 0000000000000004

// CHECK: Register SF0:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 0
// CHECK: Native RegUnit: SF0
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF
// CHECK: Native RegUnit: SF0~SW0
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF

// CHECK: Register SW0:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 1
// CHECK: SubReg sub_f16 = SW0_LO16
// CHECK: RegUnit SW0_LO16 : SW0_LO16
// CHECK: SubReg sub_i16 = SW0_HI16
// CHECK: RegUnit SW0_HI16 : SW0_HI16
// CHECK: Native RegUnit: SF0~SW0
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF
// CHECK: Native RegUnit: SW0_LO16
// CHECK: LaneMask Value: 0000000000000001
// CHECK: Native RegUnit: SW0_HI16
// CHECK: LaneMask Value: 0000000000000002

// CHECK: Register SX0:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 1
// CHECK: SubReg sub_f16 = SW0_LO16
// CHECK: RegUnit SW0_LO16 : SW0_LO16
// CHECK: SubReg sub_f32 = SW0
// CHECK: RegUnit SW0 : SF0~SW0
// CHECK: RegUnit SW0 : SW0_LO16
// CHECK: RegUnit SW0 : SW0_HI16
// CHECK: SubReg sub_i16 = SW0_HI16
// CHECK: RegUnit SW0_HI16 : SW0_HI16
// CHECK: SubReg sub_i32 = SF0
// CHECK: RegUnit SF0 : SF0
// CHECK: RegUnit SF0 : SF0~SW0
// CHECK: Native RegUnit: SF0
// CHECK: LaneMask Value: 0000000000000004
// CHECK: Native RegUnit: SF0~SW0
// CHECK: LaneMask Value: 0000000000000004
// CHECK: Native RegUnit: SW0_LO16
// CHECK: LaneMask Value: 0000000000000001
// CHECK: Native RegUnit: SW0_HI16
// CHECK: LaneMask Value: 0000000000000002

// CHECK: Register SW0_HI16:
// CHECK: CostPerUse: 0
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 0
// CHECK: Native RegUnit: SW0_HI16
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF

// CHECK: Register SW0_LO16:
// CHECK: CostPerUse: 0
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 0
// CHECK: Native RegUnit: SW0_LO16
// CHECK: LaneMask Value: FFFFFFFFFFFFFFFF
51 changes: 39 additions & 12 deletions llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Original file line number Diff line number Diff line change
@@ -424,20 +424,36 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
// These units correspond to the maximal cliques in the register overlap
// graph which is optimal.
//
// When there is ad hoc aliasing, we simply create one unit per edge in the
// undirected ad hoc aliasing graph. Technically, we could do better by
// identifying maximal cliques in the ad hoc graph, but cliques larger than 2
// are extremely rare anyway (I've never seen one), so we don't bother with
// the added complexity.
// When there is ad hoc aliasing, while we create one unit per edge in the
// undirected ad hoc aliasing graph to represent aliasing, one unit per each
// node leaf register is needed extra to identify them uniquely, in case these
// aliasing register are used as subregister(with disjoint lanemasks) to have
// an accurate lanemask generation for these leaf register.
// For example, In VE, SX0 is made out of disjoint subregister SW0 & SF0
// respectively, where SF0 is an alias for SW0. So while 2 register units will
// uniquely define these 2 subregister, the shared register unit will account
// for aliasing.
//
// Technically, we could do better by identifying maximal cliques in the ad
// hoc graph, but cliques larger than 2 are extremely rare anyway (I've never
// seen one), so we don't bother with the added complexity.
//
// Create a RegUnit for leaf register that uniquely defines it, which has
// explicit alias registers.
if (!ExplicitAliases.empty())
RegUnits.set(RegBank.newRegUnit(this));
for (CodeGenRegister *AR : ExplicitAliases) {
// Only visit each edge once.
if (AR->SubRegsComplete)
continue;
// Create a RegUnit representing this alias edge, and add it to both
// registers.
unsigned Unit = RegBank.newRegUnit(this, AR);
RegUnits.set(Unit);
AR->RegUnits.set(Unit);
unsigned SharedUnit = RegBank.newRegUnit(this, AR);
RegUnits.set(SharedUnit);
AR->RegUnits.set(SharedUnit);

// Create a RegUnit that uniquely defines the alias leaf register nodes.
AR->RegUnits.set(RegBank.newRegUnit(AR));
}

// Finally, create units for leaf registers without ad hoc aliases. Note that
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As an alternative implementation, could you simply move this block before the "Absent any ad hoc aliasing..." block?

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Why so? Because the handling of leaf register without ad hoc aliasing is really happening after this from line 456 if you see!

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The current logic is:

  1. Inherit regunits from subregs.
  2. Add a regunit for each alias.
  3. If we have no regunits after #⁠1 and #⁠2, it must be a leaf without aliases. Give it a new unique regunit.

I am suggesting swapping #⁠2 and #⁠3:

  1. Inherit regunits from subregs.
  2. If we have no regunits after #⁠1, it must be a leaf. Give it a new unique regunit.
  3. Add a regunit for each alias.

I think this gives the desired behavior.

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I am suggesting swapping #⁠2 and #⁠3:

This won't do as suppose intially once sw0 got regunit SW0 & SW0-SF0 (after step 2 and 3), at the same time in its step2, sf0 will get its regunit SW0-SF0. So when it comes to register sf0, its step2 (only if regunit empty) to give its unique regunit SW0.

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I see, but it is pretty easy to fix that problem. See #139526

@@ -2669,12 +2685,23 @@ CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) {
return BV;
}

void CodeGenRegBank::printRegUnitNames(ArrayRef<unsigned> Units) const {
for (unsigned Unit : Units) {
void CodeGenRegBank::printRegUnitName(unsigned Unit) const {
if (Unit < NumNativeRegUnits)
dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
else
dbgs() << " #" << Unit;

if (RegUnits[Unit].Roots[1]) {
if (Unit < NumNativeRegUnits)
dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
dbgs() << '~' << RegUnits[Unit].Roots[1]->getName();
else
dbgs() << " #" << Unit;
dbgs() << "~#" << Unit;
}
}

void CodeGenRegBank::printRegUnitNames(ArrayRef<unsigned> Units) const {
for (unsigned Unit : Units) {
printRegUnitName(Unit);
}
dbgs() << '\n';
}
3 changes: 3 additions & 0 deletions llvm/utils/TableGen/Common/CodeGenRegisters.h
Original file line number Diff line number Diff line change
@@ -799,6 +799,9 @@ class CodeGenRegBank {
RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }

// Helper function to print information about a register unit.
void printRegUnitName(unsigned Unit) const;

std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }

const std::list<CodeGenRegisterClass> &getRegClasses() const {
14 changes: 14 additions & 0 deletions llvm/utils/TableGen/RegisterInfoEmitter.cpp
Original file line number Diff line number Diff line change
@@ -1933,6 +1933,20 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
for (auto &[SubIdx, SubReg] : R.getSubRegs()) {
OS << "\tSubReg " << SubIdx->getName() << " = " << SubReg->getName()
<< '\n';
for (const auto &Unit : SubReg->getNativeRegUnits()) {
OS << "\tRegUnit " << SubReg->getName() << " : ";
RegBank.printRegUnitName(Unit);
OS << '\n';
}
}
const auto &RUMasks = R.getRegUnitLaneMasks();
unsigned u = 0;
for (const auto &Unit : R.getNativeRegUnits()) {
OS << "\tNative RegUnit: ";
RegBank.printRegUnitName(Unit);
OS << '\n';
OS << "\tLaneMask Value: " << PrintLaneMask(RUMasks[u]) << '\n';
++u;
}
}
}
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