Skip to content

[GISel][AArch64] Added more efficient lowering of Bitreverse #139233

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
May 13, 2025
Merged

[GISel][AArch64] Added more efficient lowering of Bitreverse #139233

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
8494424
[GISel][AArch64] Added more efficient lowering for bitreverse of vari…
jyli0116 May 8, 2025
c1ce7b7
[GISel][AArch64] Handles bitreverse as i8 vector type if legal
jyli0116 May 12, 2025
c1035dc
[GISel][AArch64] Add unit tests for types smaller than i8
jyli0116 May 12, 2025
07e1d8b
[AArch64][GIsel] Added vector check on bitreverse lowering
jyli0116 May 12, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
[GISel][AArch64] Add unit tests for types smaller than i8
  • Loading branch information
@jyli0116
jyli0116 committed May 12, 2025
commit c1035dccd00eff41a34ec616c60f22d0f4bc6ca5
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8993,8 +8993,8 @@ LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
LLT VTy = LLT::fixed_vector(VSize / 8, 8);

if (LI.isLegal({TargetOpcode::G_BITREVERSE, {VTy, VTy}})) {
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is it worth checking that [Elt]Size % 8 == 0 too?

// If bitreverse is legal for i8 vector of the same size, then handle
// with bswap and cast to i8 vector types.
// If bitreverse is legal for i8 vector of the same size, then cast
// to i8 vector type.
// e.g. v4s32 -> v16s8
auto BSWAP = MIRBuilder.buildBSwap(SrcTy, Src);
auto Cast = MIRBuilder.buildBitcast(VTy, BSWAP);
Expand Down
24 changes: 24 additions & 0 deletions llvm/test/CodeGen/AArch64/bitreverse.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,30 @@ define i64 @g_64(i64 %a) {
ret i64 %b
}

declare <16 x i3> @llvm.bitreverse.v16i3(<16 x i3>) readnone

define <16 x i3> @g_vec_16x3(<16 x i3> %a) {
; CHECK-LABEL: g_vec_16x3:
; CHECK: // %bb.0:
; CHECK-NEXT: rbit v0.16b, v0.16b
; CHECK-NEXT: ushr v0.16b, v0.16b, #5
; CHECK-NEXT: ret
%b = call <16 x i3> @llvm.bitreverse.v16i3(<16 x i3> %a)
ret <16 x i3> %b
}

declare <16 x i4> @llvm.bitreverse.v16i4(<16 x i4>) readnone

define <16 x i4> @g_vec_16x4(<16 x i4> %a) {
; CHECK-LABEL: g_vec_16x4:
; CHECK: // %bb.0:
; CHECK-NEXT: rbit v0.16b, v0.16b
; CHECK-NEXT: ushr v0.16b, v0.16b, #4
; CHECK-NEXT: ret
%b = call <16 x i4> @llvm.bitreverse.v16i4(<16 x i4> %a)
ret <16 x i4> %b
}

declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>) readnone

define <8 x i8> @g_vec(<8 x i8> %a) {
Expand Down
Loading