[RISCV] Add a couple of more compress patterns for QC_E_ADDI

[svs-quic]

Compress QC_E_ADDI to C_MV/C_ADDI16SP when possible.

[llvmbot]

@llvm/pr-subscribers-mc

Author: Sudharsan Veeravalli (svs-quic)

Changes

Compress QC_E_ADDI to C_MV/C_ADDI16SP when possible.

---

Full diff: https://github.com/llvm/llvm-project/pull/139734.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+4)
• (modified) llvm/test/MC/RISCV/xqcilia-valid.s (+10)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 49c2922fdbcff..57c1e999ac366 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1436,4 +1436,8 @@ def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
                   (C_ADDI GPRNoX0:$rs1, simm6nonzero:$imm)>;
 def : CompressPat<(QC_E_ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
                   (C_ANDI GPRC:$rs1, simm6:$imm)>;
+def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
+                  (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+def : CompressPat<(QC_E_ADDI X2, X2, simm10_lsb0000nonzero:$imm),
+                  (C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
 } // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]
diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s
index 1e4f855cb2b47..169edc42da697 100644
--- a/llvm/test/MC/RISCV/xqcilia-valid.s
+++ b/llvm/test/MC/RISCV/xqcilia-valid.s
@@ -92,3 +92,13 @@ qc.e.addi x5, x5, 20
 # CHECK-NOALIAS: c.andi s1, -10
 # CHECK-ENC: encoding: [0xd9,0x98]
 qc.e.andi x9, x9, -10
+
+# CHECK-ALIAS: mv t0, t1
+# CHECK-NOALIAS: c.mv t0, t1
+# CHECK-ENC: encoding: [0x9a,0x82]
+qc.e.addi x5, x6, 0
+
+# CHECK-ALIAS: addi sp, sp, 48
+# CHECK-NOALIAS: c.addi16sp sp, 48
+# CHECK-ENC: encoding: [0x45,0x61]
+qc.e.addi x2, x2, 48

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)

Changes

Compress QC_E_ADDI to C_MV/C_ADDI16SP when possible.

---

Full diff: https://github.com/llvm/llvm-project/pull/139734.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+4)
• (modified) llvm/test/MC/RISCV/xqcilia-valid.s (+10)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 49c2922fdbcff..57c1e999ac366 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1436,4 +1436,8 @@ def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
                   (C_ADDI GPRNoX0:$rs1, simm6nonzero:$imm)>;
 def : CompressPat<(QC_E_ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
                   (C_ANDI GPRC:$rs1, simm6:$imm)>;
+def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
+                  (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+def : CompressPat<(QC_E_ADDI X2, X2, simm10_lsb0000nonzero:$imm),
+                  (C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
 } // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]
diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s
index 1e4f855cb2b47..169edc42da697 100644
--- a/llvm/test/MC/RISCV/xqcilia-valid.s
+++ b/llvm/test/MC/RISCV/xqcilia-valid.s
@@ -92,3 +92,13 @@ qc.e.addi x5, x5, 20
 # CHECK-NOALIAS: c.andi s1, -10
 # CHECK-ENC: encoding: [0xd9,0x98]
 qc.e.andi x9, x9, -10
+
+# CHECK-ALIAS: mv t0, t1
+# CHECK-NOALIAS: c.mv t0, t1
+# CHECK-ENC: encoding: [0x9a,0x82]
+qc.e.addi x5, x6, 0
+
+# CHECK-ALIAS: addi sp, sp, 48
+# CHECK-NOALIAS: c.addi16sp sp, 48
+# CHECK-ENC: encoding: [0x45,0x61]
+qc.e.addi x2, x2, 48