Cortex M SWO SWV Demux and Postprocess (Software)

Python-based continuous integration testing framework; your pull requests are more than welcome!

An abstraction library for interfacing EDA tools

Package manager and build abstraction tool for FPGA/ASIC development

SERV - The SErial RISC-V CPU

I2C controller core

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

UVM 1.2 port to Python

OpenTitan: Open source silicon root of trust

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Library for controlling DALI lighting systems

Functional Coverage and Constrained Randomization Extensions for Cocotb

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Official KiCad schematic symbol libraries for the future Kicad 5 release

Library of components for Circuit Diagram.

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

PicoRV32 - A Size-Optimized RISC-V CPU

Official KiCad Footprint Libraries for the future Kicad version 5

KiCad project templates

creating kicad footprints using python scripts

Yosys Open SYnthesis Suite