Showing 17 open source projects for "python library"

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  • 1
    CircuiTikZ Generator

    CircuiTikZ Generator

    This software is a tool for designing electronic circuits using LaTeX.

    This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library.
    Downloads: 7 This Week
    Last Update:
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  • 2
    IP-XACT 2009/2014  Platform

    IP-XACT 2009/2014 Platform

    Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files

    Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support...
    Downloads: 1 This Week
    Last Update:
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  • 3

    System Verilog Parser IEEE 1800 LRM

    IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API

    This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the users...
    Downloads: 1 This Week
    Last Update:
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  • 4

    SimFPGA

    VHDL Verification and Simulation Tool

    SimFPGA is a graphical user interface (GUI) tool designed to facilitate the simulation of VHDL projects. It enables users to select VHDL source files and testbenches, configure library and standard settings, and run simulations using GHDL. Additionally, it allows visualization of waveforms through GTKWave. SimFPGA elaborates the project files using GHDL and builds the VHDL project before simulating it. This ensures code verification without the need for additional compilation tools...
    Downloads: 0 This Week
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  • 5
    FreeCAD-PCB

    FreeCAD-PCB

    Import your PCB boards to FreeCAD

    [ENG] Mod FreeCAD-PCB allow you to import PCB boards to FreeCAD. Scope of mod: - support for many different layers, - possible to choose colours, transparency and names for each layer, - mod allows you to import IGES models with colours, - possible to show holes/vias independent. [PL] Moduł FreeCAD-PCB pozwala na importowanie płytek PCB do programu FreeCAD. Możliwości modułu: - wsparcie dla wielu różnych warstw, - wyświetlanie otworów, przelotek niezależnie od siebie, -...
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    Downloads: 6 This Week
    Last Update:
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  • 6
    MyHDL is a Python package for using Python as a hardware description and verification language.
    Downloads: 2 This Week
    Last Update:
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  • 7
    This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).
    Downloads: 0 This Week
    Last Update:
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  • 8
    Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
    Downloads: 0 This Week
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  • 9
    CAPLET

    CAPLET

    GDS visualization and parallelized capacitance extraction

    Project CAPLET is a capacitance extraction toolkit that extract capacitance at field-solver accuracy. CAPLET can directly handle GDS2 layout files into capacitance matrices in both GUI and command line interfaces. The internal extraction algorithm is specialized for VLSI interconnect structures but not exclusively, as long as the structure is of Manhattan geometry and embedded in a uniform dielectric material.
    Downloads: 0 This Week
    Last Update:
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  • 10
    RS485 C#/Python library

    RS485 C#/Python library

    RS485 library for C# and Python

    This library consists in a shared library that can be compiled on Linux and Windows. Plus, it has a C# wrapper for Windows and Python Wrapper for Linux.
    Downloads: 0 This Week
    Last Update:
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  • 11
    Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
    Downloads: 0 This Week
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  • 12
    PyPCB is a Python package for working with PCB (http://pcb.sourceforge.net) files. PyPCB can be used to create new useful tools, as footprint generators or library managers.
    Downloads: 0 This Week
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  • 13
    PhiCAD is a LGPL'd , cross-platform software intended to provide to community an eclectic suite of CAD such as EDA to solve physics problems.
    Downloads: 0 This Week
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  • 14
    An object-oriented Python Interface to Frontline PCB's Genesis 2000 CAD/CAM/CAE system.
    Downloads: 0 This Week
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  • 15
    The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
    Downloads: 0 This Week
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  • 16
    System on Chip design generator.
    Downloads: 0 This Week
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  • 17
    The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
    Downloads: 0 This Week
    Last Update:
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