Search Results for "python library"
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Showing 15 open source projects for "python library"
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Red Hat Enterprise Linux on Microsoft AzureRed Hat Enterprise Linux (RHEL) on Microsoft Azure provides a secure, reliable, and flexible foundation for your cloud infrastructure. Red Hat Enterprise Linux on Microsoft Azure is ideal for enterprises seeking to enhance their cloud environment with seamless integration, consistent performance, and comprehensive support.
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CircuiTikZ Generator
This software is a tool for designing electronic circuits using LaTeX.
This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library. -
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SimFPGA
VHDL Verification and Simulation Tool
SimFPGA is a graphical user interface (GUI) tool designed to facilitate the simulation of VHDL projects. It enables users to select VHDL source files and testbenches, configure library and standard settings, and run simulations using GHDL. Additionally, it allows visualization of waveforms through GTKWave. SimFPGA elaborates the project files using GHDL and builds the VHDL project before simulating it. This ensures code verification without the need for additional compilation tools... -
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support... -
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FreeCAD-PCB
Import your PCB boards to FreeCAD
[ENG] Mod FreeCAD-PCB allow you to import PCB boards to FreeCAD. Scope of mod: - support for many different layers, - possible to choose colours, transparency and names for each layer, - mod allows you to import IGES models with colours, - possible to show holes/vias independent. [PL] Moduł FreeCAD-PCB pozwala na importowanie płytek PCB do programu FreeCAD. Możliwości modułu: - wsparcie dla wielu różnych warstw, - wyświetlanie otworów, przelotek niezależnie od siebie, -... -
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This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).
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CAPLET
GDS visualization and parallelized capacitance extraction
Project CAPLET is a capacitance extraction toolkit that extract capacitance at field-solver accuracy. CAPLET can directly handle GDS2 layout files into capacitance matrices in both GUI and command line interfaces. The internal extraction algorithm is specialized for VLSI interconnect structures but not exclusively, as long as the structure is of Manhattan geometry and embedded in a uniform dielectric material. -
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RS485 C#/Python library
RS485 library for C# and Python
This library consists in a shared library that can be compiled on Linux and Windows. Plus, it has a C# wrapper for Windows and Python Wrapper for Linux. -
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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PyPCB is a Python package for working with PCB (http://pcb.sourceforge.net) files. PyPCB can be used to create new useful tools, as footprint generators or library managers.
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PhiCAD is a LGPL'd , cross-platform software intended to provide to community an eclectic suite of CAD such as EDA to solve physics problems.
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The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
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The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
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