Clear FPGA pins after 3 times of invalid FPGA error (#111)

It stops FPGA clock, so if FPGA returned correct response after single Invalid FPGA error, PWM output won't work.
Clear FPGA pins only before resetting MCU.

Fix static hall error detection condition (#108)

Fix static hall signal error detection (#105)

Add slow short brake parameter (#103)

Add a parameter to gradually brake on error and init.

Disabled by default and can be enabled by sending
  $SETSOFTBRAKEMS1000
  $EEPROMSAVE

Fix source voltage compensation on R6B board (#102)

Create license tarball (#97)

Create license tarball

Add minimal voltage param (#94)

Clear internal control state on error (#92)

Add initial DIO setting (#90)

* Add initial DIO setting
* Allow lowercase hex value