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Merge pull request #15 from addymoll98/Adeline
pipelined and non-piplelined working
2 parents 1e11c0f + ccded1a commit 6e831ac

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+11
-9
lines changed

3 files changed

+11
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a.exe

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instruction.txt

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@ LD X1,1000(X0)
44
SD X1,1000(X0)
55
FADD.D F2,F4,F6
66
FSUB.D F8,F8,F10
7-
FMUL.D F8,F8,F4
8-
FDIV.D F8,F8,F4
7+
FMUL.D F2,F8,F4
8+
FMUL.D F6,F8,F4
99
FSD F8,6000(X0)
1010
ADD X1,X2,X3
1111
SUB X1,X1,X3
1212
ADDI X2,X4,1
13-
SUBI X1,X2,1
13+
SUBI X1,X2,1

project1.cpp

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -758,13 +758,13 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
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|| (resstation1[i].Qj == OperandAvailable && resstation1[i].a == 2)
759759
|| (resstation1[i].Qj == OperandAvailable && resstation1[i].a == 3))
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{
761-
if (((resstation1[i].op==0 || resstation1[i].op==1)&& FUstatus[0]==-1) //check if functional unit is available
762-
|| ((resstation1[i].op==2)&&FUstatus[1]==-1)
763-
|| ((resstation1[i].op==3)&&FUstatus[2]==-1)
764-
|| ((resstation1[i].op==4 || resstation1[i].op==5)&&FUstatus[3]==-1)
765-
||((resstation1[i].op==6 || resstation1[i].op==7|| resstation1[i].op==8|| resstation1[i].op==9|| resstation1[i].op==10|| resstation1[i].op==11)&&FUstatus[4]==-1))
761+
if (inst1[resstation1[i].instNum].executeClockBegin == 0)// check if the executeclockbegin is having default value. Use instNum variable find the instruction number
766762
{
767-
if (inst1[resstation1[i].instNum].executeClockBegin == 0)// check if the executeclockbegin is having default value. Use instNum variable find the instruction number
763+
if (((resstation1[i].op==0 || resstation1[i].op==1) && FUstatus[0]==-1) //check if functional unit is available
764+
|| ((resstation1[i].op==2) && FUstatus[1]==-1)
765+
|| ((resstation1[i].op==3) && FUstatus[2]==-1)
766+
|| ((resstation1[i].op==4 || resstation1[i].op==5) && FUstatus[3]==-1)
767+
|| ((resstation1[i].op==6 || resstation1[i].op==7|| resstation1[i].op==8|| resstation1[i].op==9|| resstation1[i].op==10|| resstation1[i].op==11) && FUstatus[4]==-1))
768768
{
769769
inst1[resstation1[i].instNum].executeClockBegin = Clock;// if it is issue the current clock value as execution start cycle
770770
if(resstation1[i].op==0 || resstation1[i].op==1) //if FADD or FSUB
@@ -778,6 +778,8 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
778778
if(resstation1[i].op==6 || resstation1[i].op==7|| resstation1[i].op==8|| resstation1[i].op==9|| resstation1[i].op==10|| resstation1[i].op==11) //int functional unit
779779
FUstatus[4]=Clock+INT; //int functional unit is 1 cc
780780
}
781+
}
782+
if (inst1[resstation1[i].instNum].executeClockBegin!=0){
781783
resstation1[i].lat++;// Increment the latency to match the latency of FMUL,FADD,FSUB etc. If latency matches means that we can perform the execution
782784
int temp_operation = resstation1[i].op; // store operation type
783785
if (temp_operation == 0)// means FADD Operation

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