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pipelined and non-piplelined working #15

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Merged
merged 1 commit into from
Nov 17, 2021
Merged

pipelined and non-piplelined working #15

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6 changes: 3 additions & 3 deletions instruction.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,10 @@ LD X1,1000(X0)
SD X1,1000(X0)
FADD.D F2,F4,F6
FSUB.D F8,F8,F10
FMUL.D F8,F8,F4
FDIV.D F8,F8,F4
FMUL.D F2,F8,F4
FMUL.D F6,F8,F4
FSD F8,6000(X0)
ADD X1,X2,X3
SUB X1,X1,X3
ADDI X2,X4,1
SUBI X1,X2,1
SUBI X1,X2,1
14 changes: 8 additions & 6 deletions project1.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -758,13 +758,13 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
|| (resstation1[i].Qj == OperandAvailable && resstation1[i].a == 2)
|| (resstation1[i].Qj == OperandAvailable && resstation1[i].a == 3))
{
if (((resstation1[i].op==0 || resstation1[i].op==1)&& FUstatus[0]==-1) //check if functional unit is available
|| ((resstation1[i].op==2)&&FUstatus[1]==-1)
|| ((resstation1[i].op==3)&&FUstatus[2]==-1)
|| ((resstation1[i].op==4 || resstation1[i].op==5)&&FUstatus[3]==-1)
||((resstation1[i].op==6 || resstation1[i].op==7|| resstation1[i].op==8|| resstation1[i].op==9|| resstation1[i].op==10|| resstation1[i].op==11)&&FUstatus[4]==-1))
if (inst1[resstation1[i].instNum].executeClockBegin == 0)// check if the executeclockbegin is having default value. Use instNum variable find the instruction number
{
if (inst1[resstation1[i].instNum].executeClockBegin == 0)// check if the executeclockbegin is having default value. Use instNum variable find the instruction number
if (((resstation1[i].op==0 || resstation1[i].op==1) && FUstatus[0]==-1) //check if functional unit is available
|| ((resstation1[i].op==2) && FUstatus[1]==-1)
|| ((resstation1[i].op==3) && FUstatus[2]==-1)
|| ((resstation1[i].op==4 || resstation1[i].op==5) && FUstatus[3]==-1)
|| ((resstation1[i].op==6 || resstation1[i].op==7|| resstation1[i].op==8|| resstation1[i].op==9|| resstation1[i].op==10|| resstation1[i].op==11) && FUstatus[4]==-1))
{
inst1[resstation1[i].instNum].executeClockBegin = Clock;// if it is issue the current clock value as execution start cycle
if(resstation1[i].op==0 || resstation1[i].op==1) //if FADD or FSUB
Expand All @@ -778,6 +778,8 @@ void execute(vector<Instruction>& inst1, vector<reservationStation>& resstation1
if(resstation1[i].op==6 || resstation1[i].op==7|| resstation1[i].op==8|| resstation1[i].op==9|| resstation1[i].op==10|| resstation1[i].op==11) //int functional unit
FUstatus[4]=Clock+INT; //int functional unit is 1 cc
}
}
if (inst1[resstation1[i].instNum].executeClockBegin!=0){
resstation1[i].lat++;// Increment the latency to match the latency of FMUL,FADD,FSUB etc. If latency matches means that we can perform the execution
int temp_operation = resstation1[i].op; // store operation type
if (temp_operation == 0)// means FADD Operation
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