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fpga-assembler Public
Forked from lromor/fpga-assemblerGenerate bitstream from FPGA assembly.
C++ Apache License 2.0 UpdatedJun 25, 2025 -
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n32emu Public
Native32 reverse engineering and emulation project
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openstreetmap-carto Public
Forked from gravitystorm/openstreetmap-cartoA general-purpose OpenStreetMap mapnik style, in CartoCSS
CartoCSS Other UpdatedApr 25, 2025 -
OpenROAD-flow-scripts Public
Forked from The-OpenROAD-Project/OpenROAD-flow-scriptsOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Verilog Other UpdatedFeb 18, 2025 -
glasgow Public
Forked from GlasgowEmbedded/glasgowScots Army Knife for electronics
Python BSD Zero Clause License UpdatedNov 19, 2024 -
glasgow-archive Public
Forked from GlasgowEmbedded/archiveDocumentation archive for onboard hardware and in-tree applets of the Glasgow Interface Explorer
C UpdatedNov 15, 2024 -
nextpnr-xilinx Public
Experimental flows using nextpnr for Xilinx devices
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OpenROAD Public
Forked from The-OpenROAD-Project/OpenROADOpenROAD's unified application implementing an RTL-to-GDS Flow
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nextpnr-xilinx-meta Public
Metadata for the nextpnr-xilinx xc7 flow
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sky130_klayout_pdk Public
Forked from efabless/sky130_klayout_pdkSkywaters 130nm Klayout PDK
Python Apache License 2.0 UpdatedJun 6, 2024 -
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riscv-dbg Public
Forked from pulp-platform/riscv-dbgRISC-V Debug Support for our PULP RISC-V Cores
SystemVerilog Other UpdatedFeb 21, 2024 -
pythondata-cpu-cv32e40p Public
Forked from litex-hub/pythondata-cpu-cv32e40pPython module containing system_verilog files for cv32e40p cpu (for use with LiteX).
SystemVerilog Other UpdatedFeb 21, 2024 -
coriolis Public
Forked from lip6/coriolisCoriolis VLSI EDA Tool (LIP6)
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mapnik Public
Forked from mapnik/mapnikMapnik is an open source toolkit for developing mapping applications
C++ GNU Lesser General Public License v2.1 UpdatedDec 25, 2023 -
nextpnr Public
Forked from YosysHQ/nextpnrnextpnr portable FPGA place and route tool
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fabulous_mpd Public
Forked from RTimothyEdwards/caravel_openframe_projectExample digital project for the Efabless Caravel "openframe" harness
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FABulous Public
Forked from FPGA-Research/FABulousFabric generator and CAD tools
Verilog Apache License 2.0 UpdatedSep 5, 2023 -
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litex Public
Forked from enjoy-digital/litexBuild your hardware, easily!
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picorv32 Public
Forked from YosysHQ/picorv32PicoRV32 - A Size-Optimized RISC-V CPU
Verilog ISC License UpdatedMar 21, 2023 -
litex-boards Public
Forked from litex-hub/litex-boardsLiteX boards files