XLS: Accelerated HW Synthesis

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

Icarus Verilog

LLVM toolchain for bazel

Syzygy TB probe tool.

🍻 A CLI workflow for the administration of Mac applications distributed as binaries

🍻 Default formulae for the missing package manager for macOS

Flexible Intermediate Representation for RTL

Coroutine Co-simulation Test Bench

homebrew (macOS) packages for RISC-V toolchain

A Library of Chisel3 Tools for Digital Signal Processing

Various tests and examples for attaching DSP blocks created using dsp-tools in Chisel to a Rocket Core

Signal — Private Messenger for Windows, Mac, and Linux

new firrtl based chisel

Tiny Scala library to generate class files for the JVM

robust, optimal, and maintainable programming language

Rocket Chip Generator

Provides various testers for chisel users

Open Source Software for Developing on the Freedom E Platform

Bare Metal Compatibility Library for the Freedom Platform

Configure C++17 project files layout fast and simply.

Chisel/Firrtl execution engine

A scala based simulator for circuits described by a LoFirrtl file