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[BUG] Unable to convert output dtype from FP32 to BF16 in Group GEMM epilogue

bugSomething isn't workingSomething isn't working

CUTLASS C++

Status: Open.

#500 In intel/sycl-tla;

· sanchitintel opened on Sep 11, 2025

[FEA] Support of FP32 scales in FP8 scaledMM

Status: Open.

#456 In intel/sycl-tla;

· sanchitintel opened on Jul 4, 2025

[BUG] FP8 scaled MM has quite high latency

bugSomething isn't workingSomething isn't working

Status: Open.

#452 In intel/sycl-tla;

· sanchitintel opened on Jul 1, 2025

Set large GRF mode in cmake

Status: Open.

#427 In intel/sycl-tla;

· rolandschulz opened on Jun 11, 2025

Test 2025.2

Status: Open.

#415 In intel/sycl-tla;

· rolandschulz opened on Jun 10, 2025

[QST] Why is U8 32x32 subgroup copy (for FP8 or 8-bit A of mixed dtype GEMMs) faster for VNNI layout than plain layout?

questionFurther information is requestedFurther information is requested

Status: Open.

#414 In intel/sycl-tla;

· sanchitintel opened on Jun 9, 2025

[FEA] Improve FP8xFP8 GEMM performance, especially for FP8_E4M3

Status: Open.

#394 In intel/sycl-tla;

· sanchitintel opened on May 27, 2025

[BUG] Incorrect result when writing example 00_pvc_gemm.cpp from CUTE

bugSomething isn't workingSomething isn't working

Status: Open.

#389 In intel/sycl-tla;

· leslie-fang-intel opened on May 26, 2025

[QST] Ambiguous error message when tuning the Tileshape

questionFurther information is requestedFurther information is requested

Status: Open.

#376 In intel/sycl-tla;

· cfgfung opened on May 14, 2025

05_pvc_gemm_with_epilogues fails verification on Windows

Status: Open.

#348 In intel/sycl-tla;

· rolandschulz opened on Apr 30, 2025

Compilation and running tests requires >8GB

Status: Open.

#343 In intel/sycl-tla;

· rolandschulz opened on Apr 30, 2025

[QST] What is the plan for adding intel-cutlass to PyTorch ?

questionFurther information is requestedFurther information is requested

Status: Open.

#286 In intel/sycl-tla;

· githubsgi opened on Mar 31, 2025