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[BUG] UF flag is not set by THMULTI DIVSQRT unit in case of tiny non-zero result that is rounded to exacly +/- b^emin

Status: Open.

#155 In openhwgroup/cvfpu;

· IhsaneTahir opened on Aug 27, 2025

[BUG F2I] FP64 to signed INT32 conversion generates erroneous NV flag

Status: Open.

#154 In openhwgroup/cvfpu;

· IhsaneTahir opened on Aug 19, 2025

PULP divsqrt unit does not produce correct results and stalls the unit with busy signal high

Status: Open.

#152 In openhwgroup/cvfpu;

· wedeha opened on Aug 14, 2025

Incorrect FCVT.W.D Signed Integer Conversion for Negative Double-Precision Input

Status: Open.

#145 In openhwgroup/cvfpu;

· Sufyan-Ahmed1 opened on Nov 26, 2024

Undefined width of reg_ena_i at fpnew_divsqrt_multi

Status: Open.

#144 In openhwgroup/cvfpu;

· redpanda3 opened on Nov 14, 2024

Out of bound signals generated by yosys

Status: Open.

#143 In openhwgroup/cvfpu;

· redpanda3 opened on Nov 6, 2024

[BUG] NX flag not correctly triggered in specific cases

Status: Open.

#139 In openhwgroup/cvfpu;

· fly-1011 opened on Aug 22, 2024

[BUG] Incorrectly set fflags: An underflow exception is triggered when the computed result is an exact subnormal number.

Status: Open.

#121 In openhwgroup/cvfpu;

· fly-1011 opened on May 18, 2024

[BUG] Incorrect fflags Set When Using fdiv Instruction to Divide by Infinity

Status: Open.

#120 In openhwgroup/cvfpu;

· fly-1011 opened on May 15, 2024

SQRT operation for FP16ALT only works when all op[n] lanes are assigned to the same input

Status: Open.

#117 In openhwgroup/cvfpu;

· selimsandal opened on May 12, 2024

[BUG] Unexpected Rounding Behavior During fsqrt.d Execution

Status: Open.

#112 In openhwgroup/cvfpu;

· youzi27 opened on Apr 22, 2024

[BUG] Incorrect Accumulation of ‘OF’ Flag in fflags After Executing fsqrt.d on Infinity

Status: Open.

#111 In openhwgroup/cvfpu;

· youzi27 opened on Apr 22, 2024