Skip to content

@YosysHQ Yosys Headquarters

Change the repository type filter

All

    Repositories list

    41 repositories

    • oss-cad-suite-build

      Public
      Multi-platform nightly builds of open source digital design and verification tools
      Shell
      •
      ISC License
      •108•1.3k•72•7•Updated Nov 30, 2025Nov 30, 2025

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •1k•4.2k•481•92•Updated Nov 29, 2025Nov 29, 2025

    • riscv-formal

      Public
      RISC-V Formal Verification Framework
      Verilog
      •
      ISC License
      •37•167•7•3•Updated Nov 29, 2025Nov 29, 2025

    • apicula

      Public
      Project Apicula 🐝: bitstream documentation for Gowin FPGAs
      Verilog
      •
      MIT License
      •81•599•18•3•Updated Nov 28, 2025Nov 28, 2025

    • abc

      Public
      ABC: System for Sequential Logic Synthesis and Formal Verification
      C
      •
      Other
      •714•30•0•3•Updated Nov 28, 2025Nov 28, 2025

    • nextpnr

      Public
      nextpnr portable FPGA place and route tool
      C++
      •
      ISC License
      •279•1.6k•109•12•Updated Nov 27, 2025Nov 27, 2025

    • prjpeppercorn-test-cases

      Public
      Project Peppercorn GateMate Test Cases
      Verilog
      •
      ISC License
      •6•10•0•0•Updated Nov 27, 2025Nov 27, 2025

    • sby

      Public
      SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
      Python
      •
      Other
      •84•480•41•10•Updated Nov 25, 2025Nov 25, 2025

    • prjpeppercorn

      Public
      Project Peppercorn - GateMate FPGA Bitstream Documentation
      Python
      •
      ISC License
      •3•30•0•0•Updated Nov 24, 2025Nov 24, 2025

    • mcy

      Public
      Mutation Cover with Yosys (MCY)
      C++
      •
      ISC License
      •14•88•1•1•Updated Nov 11, 2025Nov 11, 2025

    • eqy

      Public
      Equivalence checking with Yosys
      C++
      •
      Other
      •8•52•19•0•Updated Nov 11, 2025Nov 11, 2025

    • prjtrellis

      Public
      Documenting the Lattice ECP5 bit-stream format.
      Python
      •
      Other
      •95•433•37•14•Updated Oct 27, 2025Oct 27, 2025

    • sby-gui

      Public
      GUI for SymbiYosys
      C++
      •
      ISC License
      •5•17•7•1•Updated Oct 13, 2025Oct 13, 2025

    • nerv

      Public
      Naive Educational RISC V processor
      SystemVerilog
      •
      Other
      •16•91•2•1•Updated Oct 12, 2025Oct 12, 2025

    • icestorm

      Public
      Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
      Python
      •
      ISC License
      •234•1.1k•46•20•Updated Sep 22, 2025Sep 22, 2025

    • prjtrellis-db

      Public
      Project Trellis database
      Creative Commons Zero v1.0 Universal
      •12•13•0•1•Updated Sep 15, 2025Sep 15, 2025

    • scy

      Public
      Sequence of Covers with Yosys
      SystemVerilog
      •
      Other
      •1•6•1•0•Updated Sep 4, 2025Sep 4, 2025

    • rtlil-mlir

      Public
      Yosys RTLIL dialect for MLIR
      C++
      •
      ISC License
      •1•12•1•0•Updated Jun 12, 2025Jun 12, 2025

    • furo-ys

      Public
      A clean customizable documentation theme for Sphinx
      Sass
      •
      MIT License
      •367•1•0•0•Updated Apr 21, 2025Apr 21, 2025

    • mau

      Public
      Modular Application Utilities
      Python
      •
      ISC License
      •3•5•1•0•Updated Feb 12, 2025Feb 12, 2025

    • imctk

      Public
      Incremental Model Checking Toolkit
      Rust
      •
      Other
      •2•10•41•1•Updated Jan 30, 2025Jan 30, 2025

    • nextpnr-tests

      Public
      Verilog
      •
      ISC License
      •5•6•2•2•Updated Jan 16, 2025Jan 16, 2025

    • yosyshq.github.io

      Public
      www.yosyshq.net
      HTML
      •1•4•0•0•Updated Oct 7, 2024Oct 7, 2024

    • yosys-web

      Public
      Yosys Web Page
      HTML
      •6•2•1•0•Updated Oct 7, 2024Oct 7, 2024

    • picorv32

      Public
      PicoRV32 - A Size-Optimized RISC-V CPU
      Verilog
      •
      ISC License
      •880•3.8k•67•15•Updated Jun 27, 2024Jun 27, 2024

    • VlogHammer

      Public
      A Verilog Synthesis Regression Test
      Shell
      •11•37•0•3•Updated Mar 21, 2024Mar 21, 2024

    • setup-oss-cad-suite

      Public
      Set up your GitHub Actions workflow with a OSS CAD Suite
      TypeScript
      •
      ISC License
      •3•16•4•1•Updated Mar 21, 2024Mar 21, 2024

    • padring

      Public
      A padring generator for ASICs
      asicedachipvlsiyosys
      C++
      •
      ISC License
      •11•25•2•1•Updated May 17, 2023May 17, 2023

    • .github

      Public
      0•0•0•0•Updated Apr 4, 2023Apr 4, 2023

    • yosys-manual-build

      Public archive
      Yosys manual
      Dockerfile
      •0•1•0•0•Updated Oct 24, 2022Oct 24, 2022