Porting to kr260

Makefile

@@ -7,18 +7,20 @@ YML=$(shell find . -name '*.yml' -print)
 IOSCRIPT=rtl/includes/pulp_soc_defines.svh
 IOSCRIPT+=rtl/includes/pulp_peripheral_defines.svh
 IOSCRIPT+=rtl/includes/periph_bus_defines.svh
-IOSCRIPT+=nexys-pin-table.csv genesys2-pin-table.csv
+IOSCRIPT+=nexys-pin-table.csv genesys2-pin-table.csv kr260-pin-table.csv
 IOSCRIPT+=perdef.json
 NEXSY_XDC=emulation/core-v-mcu-nexys/constraints/Nexys-A7-100T-Master.xdc
 NEXYSA7_BITMAP?=emulation/core_v_mcu_nexys.bit
 GENESYS_XDC=emulation/core-v-mcu-nexys/constraints/Genesys2-Master.xdc
+KR260_XDC=emulation/core-v-mcu-kr260/constraints/KR260-Master.xdc
 
 IOSCRIPT_OUT=rtl/core-v-mcu/top/pad_control.sv
 IOSCRIPT_OUT+=rtl/includes/pulp_peripheral_defines.svh
 IOSCRIPT_OUT+=rtl/includes/periph_bus_defines.svh
 IOSCRIPT_OUT+=core-v-mcu-config.h
 IOSCRIPT_NEXSY=emulation/core-v-mcu-nexys/constraints/core-v-mcu-pin-assignment.xdc
 IOSCRIPT_GENESY+=emulation/core-v-mcu-genesys2/constraints/core-v-mcu-pin-assignment.xdc
+IOSCRIPT_KR260=emulation/core-v-mcu-kr260/constraints/core-v-mcu-pin-assignment.xdc
 
 
 #Must also change the localparam 'L2_BANK_SIZE' in pulp_soc.sv accordingly
@@ -34,6 +36,7 @@ help:
 			@echo "sw:             generate C header files (in ./sw)"
 			@echo "nexys-emul:     generate bitstream for Nexys-A7-100T emulation)"
 			@echo "genesys-emul:   generate bitstream for Genesys2 emulation)"
+			@echo "kr260-emul:     generate bitstream for KR260 emulation)"
 			@echo "buildsim:       build for Questa sim"
 			@echo "sim:            run Questa sim"
 			@echo "build-vivado:   build for Vivado simulation (xelab)"
@@ -196,6 +199,45 @@ genesys-emul:
 				cp ./build/openhwgroup.org_systems_core-v-mcu_0/genesys2-vivado/openhwgroup.org_systems_core-v-mcu_0.runs/impl_1/core_v_mcu_genesys2.bit emulation/core_v_mcu_genesys2.bit
 
 
+.PHONEY: kr260-emul
+kr260-emul:
+				@echo "*************************************"
+				@echo "*                                   *"
+				@echo "* setting up kr260 specific files   *"
+				@echo "*                                   *"
+				@echo "*************************************"
+				mkdir -p emulation/core-v-mcu-kr260/rtl
+				python3 util/ioscript.py\
+					--soc-defines rtl/includes/pulp_soc_defines.svh\
+					--peripheral-defines rtl/includes/pulp_peripheral_defines.svh\
+					--periph-bus-defines rtl/includes/periph_bus_defines.svh\
+					--pin-table kr260-pin-table.csv\
+					--perdef-json perdef.json\
+					--pad-control rtl/core-v-mcu/top/pad_control.sv\
+					--emulation-toplevel core_v_mcu_kr260\
+					--xilinx-core-v-mcu-sv emulation/core-v-mcu-kr260/rtl/core_v_mcu_kr260.v\
+					--input-xdc emulation/core-v-mcu-kr260/constraints/KR260-Master.xdc\
+					--output-xdc emulation/core-v-mcu-kr260/constraints/core-v-mcu-pin-assignment.xdc
+				util/format-verible
+				@echo "*************************************"
+				@echo "*                                   *"
+				@echo "* running Vivado                    *"
+				@echo "*                                   *"
+				@echo "*************************************"
+				(\
+					export BOARD=kr260;\
+					export BOARD_CLOCK_MHZ=25;\
+					export XILINX_PART=xck26-sfvc784-2lv-c;\
+					export XILINX_BOARD=xilinx.com:kr260_som:part0:1.1;\
+					export FC_CLK_PERIOD_NS=125;\
+					export PER_CLK_PERIOD_NS=125;\
+					export FPGA_CLK_PERIOD_NS=125;\
+					export SLOW_CLK_PERIOD_NS=4000;\
+					fusesoc --cores-root . run --target=kr260 --setup --build openhwgroup.org:systems:core-v-mcu\
+				) 2>&1 | tee lint.log
+				cp ./build/openhwgroup.org_systems_core-v-mcu_0/kr260-vivado/openhwgroup.org_systems_core-v-mcu_0.runs/impl_1/core_v_mcu_kr260.bit emulation/core_v_mcu_kr260.bit
+
+
 .PHONY:docs
 docs:
 				(cd docs; make)

core-v-mcu-emul.core

@@ -45,6 +45,17 @@ filesets:
     - emulation/core-v-mcu-nexys/tcl/flatten.tcl
     file_type: tclSource
 
+  kr260-xdc:
+    files:
+    - emulation/core-v-mcu-kr260/constraints/core-v-mcu-pin-assignment.xdc
+    file_type: xdc
+
+  kr260-cfg:
+    files:
+    - emulation/core-v-mcu-kr260/tcl/common.tcl
+    - emulation/core-v-mcu-kr260/tcl/flatten.tcl
+    file_type: tclSource
+
   xilinx-ips:
     files:
     - emulation/xilinx/ips/xilinx_clk_mngr.tcl
@@ -93,3 +104,17 @@ targets:
       vivado:
         part: xc7a100tcsg324-1
     toplevel: xilinx_core_v_mcu
+
+  kr260:
+    <<: *default
+    default_tool: vivado
+    description: Xilinx KR260 board
+    parameters:
+    - PULP_FPGA_EMUL=true
+    filesets_append:
+    - kr260-cfg
+    - kr260-xdc
+    tools:
+      vivado:
+        part: xck26-sfvc784-2lv-c
+    toplevel: xilinx_core_v_mcu

core-v-mcu.core

@@ -132,6 +132,11 @@ filesets:
     - emulation/core-v-mcu-genesys2/ips/xilinx_clk_mngr.tcl
     file_type: tclSource
 
+  kr260-ips:
+    files:
+    - emulation/xilinx/ips/xilinx_clk_mngr.tcl
+    file_type: tclSource
+
   xilinx-ips:
     files:
 #    - emulation/xilinx/ips/xilinx_slow_clk_mngr.tcl
@@ -189,6 +194,17 @@ filesets:
     - emulation/core-v-mcu-nexys/constraints/core-v-mcu-pin-assignment.xdc
     file_type: xdc
 
+  kr260-rtl:
+    files:
+    - emulation/core-v-mcu-kr260/rtl/core_v_mcu_kr260.v
+    - emulation/xilinx/rtl/fpga_clk_gen.sv
+    file_type: systemVerilogSource
+
+  kr260-xdc:
+    files:
+    - emulation/core-v-mcu-kr260/constraints/core-v-mcu-pin-assignment.xdc
+    file_type: xdc
+
   xilinx-tcl:
     files:
     - emulation/xilinx/tcl/common.tcl
@@ -363,3 +379,22 @@ targets:
       vivado:
         part: xc7k325tffg900-2
     toplevel: core_v_mcu_genesys2
+
+  kr260:
+    <<: *default_target
+    default_tool: vivado
+    description: Xilinx KR260 Board
+    parameters:
+    - PULP_FPGA_EMUL=true
+    filesets_append:
+    - kr260-ips
+    - xilinx-ips
+    - xilinx-tcl
+    - emulation-rtl
+    - kr260-rtl
+    - kr260-xdc
+    - rom_init
+    tools:
+      vivado:
+        part: xck26-sfvc784-2lv-c
+    toplevel: core_v_mcu_kr260

emulation/core-v-mcu-kr260/constraints/KR260-Master.xdc

@@ -0,0 +1,70 @@
+## This file is a general .xdc for the KR260
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+#set_property -dict { PACKAGE_PIN C3    IOSTANDARD LVCMOS18 } [get_ports { CLK100MHZ }];
+
+
+## LEDs
+#set_property -dict { PACKAGE_PIN F8   IOSTANDARD LVCMOS18 } [get_ports { LED[0] }];
+#set_property -dict { PACKAGE_PIN E8   IOSTANDARD LVCMOS18 } [get_ports { LED[1] }];
+
+##Pmod Headers
+##Pmod Header J2
+#set_property -dict { PACKAGE_PIN H12   IOSTANDARD LVCMOS33 } [get_ports { J2[1] }];
+#set_property -dict { PACKAGE_PIN E10   IOSTANDARD LVCMOS33 } [get_ports { J2[3] }];
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { J2[5] }];
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { J2[7] }];
+#set_property -dict { PACKAGE_PIN B10   IOSTANDARD LVCMOS33 } [get_ports { J2[2] }];
+#set_property -dict { PACKAGE_PIN E12   IOSTANDARD LVCMOS33 } [get_ports { J2[4] }];
+#set_property -dict { PACKAGE_PIN D11   IOSTANDARD LVCMOS33 } [get_ports { J2[6] }];
+#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { J2[8] }];
+
+##Pmod Header J18
+#set_property -dict { PACKAGE_PIN J11   IOSTANDARD LVCMOS33 } [get_ports { J18[1] }];
+#set_property -dict { PACKAGE_PIN J10   IOSTANDARD LVCMOS33 } [get_ports { J18[3] }];
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { J18[5] }];
+#set_property -dict { PACKAGE_PIN K12   IOSTANDARD LVCMOS33 } [get_ports { J18[7] }];
+#set_property -dict { PACKAGE_PIN H11   IOSTANDARD LVCMOS33 } [get_ports { J18[2] }];
+#set_property -dict { PACKAGE_PIN G10   IOSTANDARD LVCMOS33 } [get_ports { J18[4] }];
+#set_property -dict { PACKAGE_PIN F12   IOSTANDARD LVCMOS33 } [get_ports { J18[6] }];
+#set_property -dict { PACKAGE_PIN F11   IOSTANDARD LVCMOS33 } [get_ports { J18[8] }];
+
+##Pmod Header J19
+#set_property -dict { PACKAGE_PIN AE12    IOSTANDARD LVCMOS33 } [get_ports { J19[1] }];
+#set_property -dict { PACKAGE_PIN AF12    IOSTANDARD LVCMOS33 } [get_ports { J19[3] }];
+#set_property -dict { PACKAGE_PIN AG10    IOSTANDARD LVCMOS33 } [get_ports { J19[5] }];
+#set_property -dict { PACKAGE_PIN AH10    IOSTANDARD LVCMOS33 } [get_ports { J19[7] }];
+#set_property -dict { PACKAGE_PIN AF11    IOSTANDARD LVCMOS33 } [get_ports { J19[2] }];
+#set_property -dict { PACKAGE_PIN AG11    IOSTANDARD LVCMOS33 } [get_ports { J19[4] }];
+#set_property -dict { PACKAGE_PIN AH12    IOSTANDARD LVCMOS33 } [get_ports { J19[6] }];
+#set_property -dict { PACKAGE_PIN AH11    IOSTANDARD LVCMOS33 } [get_ports { J19[8] }];
+
+##Pmod Header J20
+#set_property -dict { PACKAGE_PIN AC12    IOSTANDARD LVCMOS33 } [get_ports { J20[1] }];
+#set_property -dict { PACKAGE_PIN AD12    IOSTANDARD LVCMOS33 } [get_ports { J20[3] }];
+#set_property -dict { PACKAGE_PIN AE10    IOSTANDARD LVCMOS33 } [get_ports { J20[5] }];
+#set_property -dict { PACKAGE_PIN AF10    IOSTANDARD LVCMOS33 } [get_ports { J20[7] }];
+#set_property -dict { PACKAGE_PIN AD11    IOSTANDARD LVCMOS33 } [get_ports { J20[2] }];
+#set_property -dict { PACKAGE_PIN AD10    IOSTANDARD LVCMOS33 } [get_ports { J20[4] }];
+#set_property -dict { PACKAGE_PIN AA11    IOSTANDARD LVCMOS33 } [get_ports { J20[6] }];
+#set_property -dict { PACKAGE_PIN AA10    IOSTANDARD LVCMOS33 } [get_ports { J20[8] }];
+
+##Raspberry Pi connector 2x20
+#set_property -dict { PACKAGE_PIN AG14   IOSTANDARD LVCMOS33 } [get_ports { J21[7] }];
+#set_property -dict { PACKAGE_PIN AB14   IOSTANDARD LVCMOS33 } [get_ports { J21[11] }];
+#set_property -dict { PACKAGE_PIN AB9    IOSTANDARD LVCMOS33 } [get_ports { J21[13] }];
+#set_property -dict { PACKAGE_PIN Y12    IOSTANDARD LVCMOS33 } [get_ports { J21[15] }];
+#set_property -dict { PACKAGE_PIN W14    IOSTANDARD LVCMOS33 } [get_ports { J21[8] }];
+#set_property -dict { PACKAGE_PIN W13    IOSTANDARD LVCMOS33 } [get_ports { J21[10] }];
+#set_property -dict { PACKAGE_PIN Y14    IOSTANDARD LVCMOS33 } [get_ports { J21[12] }];
+#set_property -dict { PACKAGE_PIN AA12   IOSTANDARD LVCMOS33 } [get_ports { J21[16] }];
+#set_property -dict { PACKAGE_PIN W12    IOSTANDARD LVCMOS33 } [get_ports { J21[38] }];
+#set_property -dict { PACKAGE_PIN W11    IOSTANDARD LVCMOS33 } [get_ports { J21[40] }];
+#set_property -dict { PACKAGE_PIN AH14   IOSTANDARD LVCMOS33 } [get_ports { J21[29] }];
+#set_property -dict { PACKAGE_PIN AG13   IOSTANDARD LVCMOS33 } [get_ports { J21[31] }];
+#set_property -dict { PACKAGE_PIN AB13   IOSTANDARD LVCMOS33 } [get_ports { J21[33] }];
+#set_property -dict { PACKAGE_PIN Y13    IOSTANDARD LVCMOS33 } [get_ports { J21[35] }];
+#set_property -dict { PACKAGE_PIN AA8    IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #J21[22]

emulation/core-v-mcu-kr260/constraints/core-v-mcu-pin-assignment.xdc

@@ -0,0 +1,71 @@
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {s_tck}]
+## This file is a general .xdc for the KR260
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+set_property -dict { PACKAGE_PIN C3 IOSTANDARD LVCMOS18 } [get_ports { ref_clk }];
+
+
+## LEDs
+set_property -dict { PACKAGE_PIN F8 IOSTANDARD LVCMOS18 } [get_ports { xilinx_io[11] }];
+#set_property -dict { PACKAGE_PIN E8   IOSTANDARD LVCMOS18 } [get_ports { LED[1] }];
+
+##Pmod Headers
+##Pmod Header J2
+set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[37] }];
+set_property -dict { PACKAGE_PIN E10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[38] }];
+set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[39] }];
+set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[40] }];
+set_property -dict { PACKAGE_PIN B10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[41] }];
+set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[42] }];
+set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[43] }];
+set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[44] }];
+
+##Pmod Header J18
+#set_property -dict { PACKAGE_PIN J11   IOSTANDARD LVCMOS33 } [get_ports { J18[1] }];
+set_property -dict { PACKAGE_PIN J10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[9] }];
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[10] }];
+set_property -dict { PACKAGE_PIN K12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[12] }];
+set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[3] }];
+set_property -dict { PACKAGE_PIN G10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[1] }];
+set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[2] }];
+set_property -dict { PACKAGE_PIN F11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[0] }];
+
+##Pmod Header J19
+set_property -dict { PACKAGE_PIN AE12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[21] }];
+set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[22] }];
+set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[23] }];
+set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[24] }];
+set_property -dict { PACKAGE_PIN AF11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[25] }];
+set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[26] }];
+set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[27] }];
+set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[28] }];
+
+##Pmod Header J20
+set_property -dict { PACKAGE_PIN AC12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[29] }];
+set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[30] }];
+set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[31] }];
+set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[32] }];
+set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[33] }];
+set_property -dict { PACKAGE_PIN AD10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[34] }];
+set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[35] }];
+set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[36] }];
+
+##Raspberry Pi connector 2x20
+set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[13] }];
+set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[14] }];
+set_property -dict { PACKAGE_PIN AB9 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[15] }];
+set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[16] }];
+set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[17] }];
+set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[18] }];
+set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[19] }];
+set_property -dict { PACKAGE_PIN AA12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[20] }];
+set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[45] }];
+set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[4] }];
+set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[7] }];
+set_property -dict { PACKAGE_PIN AG13 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[8] }];
+set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[46] }];
+set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[47] }];
+set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[6] }]; #J21[22]

emulation/core-v-mcu-kr260/constraints/core-v-mcu-timing.xdc

@@ -0,0 +1,79 @@
+#
+#
+#
+#
+#
+#
+#
+#
+
+
+### Constraint File for the KR260 board
+
+
+#######################################
+#  _______ _           _              #
+# |__   __(_)         (_)             #
+#    | |   _ _ __ ___  _ _ __   __ _  #
+#    | |  | | '_ ` _ \| | '_ \ / _` | #
+#    | |  | | | | | | | | | | | (_| | #
+#    |_|  |_|_| |_| |_|_|_| |_|\__, | #
+#                               __/ | #
+#                              |___/  #
+#######################################
+
+
+#Create constraint for the clock input of the nexys board
+create_clock -period 10.000 -name ref_clk [get_ports sys_clk]
+
+#I2S and CAM interface are not used in this FPGA port. Set constraints to
+#disable the clock
+set_case_analysis 0 i_core_v_mcu/safe_domain_i/cam_pclk_o
+set_case_analysis 0 i_core_v_mcu/safe_domain_i/i2s_slave_sck_o
+#set_input_jitter tck 1.000
+
+## JTAG
+create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck]
+set_input_jitter tck 1.000
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets s_io[8]]; # was tck_int
+
+
+# minimize routing delay
+set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi]
+set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tms]
+set_output_delay -clock tck 5.000 [get_ports pad_jtag_tdo]
+
+
+set_max_delay -to [get_ports pad_jtag_tdo] 20.000
+set_max_delay -from [get_ports pad_jtag_tms] 20.000
+set_max_delay -from [get_ports pad_jtag_tdi] 20.000
+
+
+set_max_delay -datapath_only -from [get_pins i_core_v_mcu/i_soc_domain_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_core_v_mcu/i_soc_domain_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_core_v_mcu/i_soc_domain_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_core_v_mcu/i_soc_domain_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_core_v_mcu/i_soc_domain_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_core_v_mcu/i_soc_domain_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
+
+
+# reset signal
+set_false_path -from [get_ports pad_reset_n]
+
+# Set ASYNC_REG attribute for ff synchronizers to place them closer together and
+# increase MTBF
+set_property ASYNC_REG true [get_cells i_core_v_mcu/i_soc_domain_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_core_v_mcu/i_soc_domain_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_core_v_mcu/i_soc_domain_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_core_v_mcu/i_soc_domain_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_core_v_mcu/i_soc_domain_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*]
+set_property ASYNC_REG true [get_cells i_core_v_mcu/i_soc_domain_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*]
+set_property ASYNC_REG true [get_cells i_core_v_mcu/i_soc_domain_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*]
+
+# Create asynchronous clock group between slow-clk and SoC clock. Those clocks
+# are considered asynchronously and proper synchronization regs are in place
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_core_v_mcu/safe_domain_i/i_slow_clk_gen/i_slow_clk_mngr/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins i_core_v_mcu/i_soc_domain_i/i_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcm_adv_inst/CLKOUT0]]
+
+# Create asynchronous clock group between Per Clock  and SoC clock. Those clocks
+# are considered asynchronously and proper synchronization regs are in place
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_core_v_mcu/i_soc_domain_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_core_v_mcu/i_soc_domain_i/i_clk_rst_gen/clk_soc_o]]
+
+# Create asynchronous clock group between JTAG TCK and SoC clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_core_v_mcu/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_core_v_mcu/i_soc_domain_i/i_clk_rst_gen/clk_soc_o]]

emulation/core-v-mcu-kr260/rtl/.gitignore

@@ -0,0 +1 @@
+core_v_mcu_nexys.v