GitHub - ymbelbase/Digital_Logic: This is just a school experiment project

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
random		random
RCA16Bit.vcd		RCA16Bit.vcd
Untitled Diagram.drawio		Untitled Diagram.drawio
alu.out		alu.out
alu.v		alu.v
alu_tb.v		alu_tb.v
alu_wave.vcd		alu_wave.vcd
counter.v		counter.v
counter_tb.out		counter_tb.out
counter_tb.v		counter_tb.v
counter_wave.vcd		counter_wave.vcd
decoder3to8.v		decoder3to8.v
decoder3to8.vcd		decoder3to8.vcd
decoder3to8_tb.out		decoder3to8_tb.out
decoder3to8_tb.v		decoder3to8_tb.v
decoder_tb.out		decoder_tb.out
encoder3to8.v		encoder3to8.v
encoder3to8_tb.out		encoder3to8_tb.out
encoder3to8_tb.v		encoder3to8_tb.v
mux8to1.v		mux8to1.v
mux8to1_4bit.vcd		mux8to1_4bit.vcd
mux8to1_tb.out		mux8to1_tb.out
mux8to1_tb.v		mux8to1_tb.v
priority_encoder.vcd		priority_encoder.vcd
rcaadder.v		rcaadder.v
rcaadder_tb.out		rcaadder_tb.out
rcaadder_tb.v		rcaadder_tb.v
register.v		register.v
register2.v		register2.v
register2_tb.out		register2_tb.out
register2_tb.v		register2_tb.v
register_tb.out		register_tb.out
register_tb.v		register_tb.v
register_wave.vcd		register_wave.vcd
sequence_detector.vcd		sequence_detector.vcd
shift_register_wave.vcd		shift_register_wave.vcd
state.out		state.out
state.v		state.v
state_tb.v		state_tb.v