Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V CPU Core (RV32IM)

HW Design Collateral for Caliptra RoT IP

Reconfigurable Computing Lab, DESE, Indian Institiute of Science

SystemVerilog to Verilog conversion

An incredibly small 32-bit RISC-V rv32acim CPU capable of running Linux on FPGA, and software simulations.

bitfusion verilog implementation

32-bit Superscalar RISC-V CPU

A simple superscalar out-of-order RISC-V microprocessor

PDF Reader in JavaScript