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Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Verilog 181 24 Updated Jun 28, 2021

A FPGA friendly 32 bit RISC-V CPU implementation

Assembly 2,952 482 Updated Dec 15, 2025

RISC-V CPU Core (RV32IM)

Verilog 1,603 275 Updated Sep 18, 2021
Verilog 214 45 Updated Jun 25, 2025

HW Design Collateral for Caliptra RoT IP

SystemVerilog 124 70 Updated Dec 23, 2025

Reconfigurable Computing Lab, DESE, Indian Institiute of Science

Verilog 30 5 Updated Jun 27, 2022

SystemVerilog to Verilog conversion

Haskell 688 59 Updated Nov 24, 2025

An incredibly small 32-bit RISC-V rv32acim CPU capable of running Linux on FPGA, and software simulations.

Verilog 29 5 Updated Nov 17, 2024

bitfusion verilog implementation

Verilog 12 Updated Feb 21, 2022

32-bit Superscalar RISC-V CPU

Verilog 1,157 199 Updated Sep 18, 2021
Verilog 1 Updated Dec 18, 2024

A simple superscalar out-of-order RISC-V microprocessor

SystemVerilog 232 21 Updated Feb 24, 2025

PDF Reader in JavaScript

JavaScript 52,526 10,539 Updated Dec 23, 2025