Fix some details, make it can be simulated by verilator #15
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Adjust the arithmetic bit width, now it can be simulated by verilator
Adjust the arithmetic bit width, now it can be simulated by verilator
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There is a bit-width error on the main module, and a peculiar error which can be repaired simply by adding some comment statements that can have an effect on verilator's compiler.
Now we can use verilator to simulator these modules directly