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Pull requests: OpenXiangShan/XiangShan
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feat(Bpu): add BpTrace
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
module: tool
difftest, gsim, XSpdb, Makefiles, scripts, etc.
topic: verification
To make function/performance verification easier
fix(tage): BaseTable use Queue and fix some typos
#5090
opened Sep 30, 2025 by
TheKiteRunner24
•
Draft
fix(tage): fix providerIdxOH
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
fix(amocas): amocas should not respond to interrupts and flushpipe
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
note: do not squash
(PR) For maintainer: please use rebase-and-merge instead of squash-and-merge
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5084
opened Sep 28, 2025 by
Anzooooo
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feat(writebuffer): support multiple write port write
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
fix simfrontend and prefetch assert
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
module: tool
difftest, gsim, XSpdb, Makefiles, scripts, etc.
note: do not squash
(PR) For maintainer: please use rebase-and-merge instead of squash-and-merge
topic: usability
To make XiangShan easier to use
#5080
opened Sep 28, 2025 by
Anzooooo
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fix(Closecompress): when rob compress close, fusion which cross two ftq should be cancompressed
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
timing(alu): fix alu timing to support 6 alu
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
topic: timing
To fix bad timing
feat(perfcct): Add disassembler query and fixes
module: tool
difftest, gsim, XSpdb, Makefiles, scripts, etc.
#5077
opened Sep 26, 2025 by
cyyself
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refactor(predecode): use branchAttribute instead of brType
module: backend
Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: code quality
To make code more readable & maintainable
refactor(Bpu): use compareMatrix
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: code quality
To make code more readable & maintainable
fix(Bitmap): fix bitmap check result wakeup
l0BitmapReg
logic
#5073
opened Sep 26, 2025 by
yxtx1994
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fix(Bpu): remove abtbMeta from BpuMeta and add FastTrain IO
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: code quality
To make code more readable & maintainable
fix(CSR, NMI): fix the logic for gating Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
nmi
module: backend
feat(ittage): add writeBuffer & resolve training
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
note: do not squash
(PR) For maintainer: please use rebase-and-merge instead of squash-and-merge
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
feat(ifu): merge predChecker two-fetch writeback into a single redirect interface.
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: code quality
To make code more readable & maintainable
feat(sc): add sc skeleton
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
feat(abtb): support fast predict when s3 override
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
topic: performance
To improve performance
test Bpu s3 override
module: frontend
Bpu, Ftq, Ifu, ICache, IBuffer
note: testing
(PR) For maintainer: this is for CI test, do not merge
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
perf(pf): add berti prefetch
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: performance
To improve performance
fix(LoadUnit): Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: funtionality
To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
tlb.req.kill
is only valid when s1_valid
module: memory
timing(LoadQueueReplay): move needReplay generation to LDU
module: memory
Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
topic: timing
To fix bad timing
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