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[nrf fromtree] modules: CMSIS_6: fix path and use it for TF-M and Cortex-M #2914

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Merged
merged 2 commits into from
May 30, 2025
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[nrf fromtree] modules: CMSIS_6: fix path and use it for TF-M and Cortex-M #2914

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d5b57f1
[nrf fromtree] modules: CMSIS_6: fix path and use it for TF-M
wearyzen Apr 29, 2025
78f9681
[nrf fromtree] modules: CMSIS_6: Switch to CMSIS_6 for Cortex-M
wearyzen Apr 29, 2025
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2 changes: 1 addition & 1 deletion modules/cmsis/CMakeLists.txt
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Expand Up @@ -3,6 +3,6 @@

add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR} cmsis)

if(CONFIG_CPU_CORTEX_M OR CONFIG_CPU_AARCH32_CORTEX_A OR CONFIG_CPU_AARCH32_CORTEX_R)
if(CONFIG_CPU_AARCH32_CORTEX_A OR CONFIG_CPU_AARCH32_CORTEX_R)
zephyr_include_directories(.)
endif()
16 changes: 0 additions & 16 deletions modules/cmsis/Kconfig
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Expand Up @@ -8,7 +8,6 @@ config HAS_CMSIS_CORE
bool
select HAS_CMSIS_CORE_A if CPU_AARCH32_CORTEX_A
select HAS_CMSIS_CORE_R if CPU_AARCH32_CORTEX_R
select HAS_CMSIS_CORE_M if CPU_CORTEX_M

if HAS_CMSIS_CORE

Expand All @@ -18,19 +17,4 @@ config HAS_CMSIS_CORE_A
config HAS_CMSIS_CORE_R
bool

config HAS_CMSIS_CORE_M
bool

config CMSIS_M_CHECK_DEVICE_DEFINES
bool "Check device defines"
default n
depends on HAS_CMSIS_CORE_M
help
This options enables the validation of CMSIS configuration flags.

config CMSIS_CORE_HAS_SYSTEM_CORE_CLOCK
bool
help
Enable this option if CMSIS SystemCoreClock symbols is available.

endif
4 changes: 1 addition & 3 deletions modules/cmsis/cmsis_core.h
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Expand Up @@ -6,9 +6,7 @@
#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_H_
#define ZEPHYR_MODULES_CMSIS_CMSIS_H_

#if defined(CONFIG_CPU_CORTEX_M)
#include "cmsis_core_m.h"
#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R)
#if defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R)
#include "cmsis_core_a_r.h"
#endif

Expand Down
9 changes: 9 additions & 0 deletions modules/cmsis_6/CMakeLists.txt
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@@ -0,0 +1,9 @@
# Copyright (c) 2023 Nordic Semiconductor ASA
# Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
# SPDX-License-Identifier: Apache-2.0

add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR} cmsis_6)

if(CONFIG_CPU_CORTEX_M)
zephyr_include_directories(.)
endif()
28 changes: 28 additions & 0 deletions modules/cmsis_6/Kconfig
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@@ -0,0 +1,28 @@
# Copyright (c) 2016 Intel Corporation
# Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
# SPDX-License-Identifier: Apache-2.0

config ZEPHYR_CMSIS_6_MODULE
bool

config HAS_CMSIS_CORE
bool
select HAS_CMSIS_CORE_M if CPU_CORTEX_M

if HAS_CMSIS_CORE

config HAS_CMSIS_CORE_M
bool

config CMSIS_M_CHECK_DEVICE_DEFINES
bool "Check device defines"
depends on HAS_CMSIS_CORE_M
help
This options enables the validation of CMSIS configuration flags.

config CMSIS_CORE_HAS_SYSTEM_CORE_CLOCK
bool
help
Enable this option if CMSIS SystemCoreClock symbols is available.

endif
14 changes: 14 additions & 0 deletions modules/cmsis_6/cmsis_core.h
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@@ -0,0 +1,14 @@
/*
* Copyright (c) 2023 Nordic Semiconductor ASA
* Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_H_
#define ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_H_

#if defined(CONFIG_CPU_CORTEX_M)
#include "cmsis_core_m.h"
#endif

#endif /* ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_H_ */
8 changes: 4 additions & 4 deletions modules/cmsis/cmsis_core_m.h → modules/cmsis_6/cmsis_core_m.h
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@@ -1,6 +1,6 @@
/*
* Copyright (c) 2017 Nordic Semiconductor ASA
* Copyright (c) 2023 Arm Limited
* Copyright 2023,2025 Arm Limited and/or its affiliates <[email protected]>
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand All @@ -12,8 +12,8 @@
* This header contains the interface to the ARM CMSIS Core headers.
*/

#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_H_
#define ZEPHYR_MODULES_CMSIS_CMSIS_M_H_
#ifndef ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_H_
#define ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_H_

#if defined(CONFIG_CMSIS_M_CHECK_DEVICE_DEFINES) && CONFIG_CMSIS_M_CHECK_DEVICE_DEFINES == 1U
#define __CHECK_DEVICE_DEFINES 1U
Expand Down Expand Up @@ -41,7 +41,7 @@
*/
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && \
(__VTOR_PRESENT != CONFIG_CPU_CORTEX_M_HAS_VTOR)
#error "__VTOR_PRESENT and CONFIG_CPU_CORTEX_M_HAS_VTOR are not set to the same value."

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modules/cmsis_6/cmsis_core_m.h:44 
-
 /* VTOR is only optional on armv6-m and armv8-m baseline. __VTOR_PRESENT is often
  * left undefined on platform where it is not optional.
  */
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && \
-	(__VTOR_PRESENT != CONFIG_CPU_CORTEX_M_HAS_VTOR)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && (__VTOR_PRESENT != CONFIG_CPU_CORTEX_M_HAS_VTOR)
#endif

/* Some platform’s sdk incorrectly define __DSP_PRESENT for Cortex-M4 & Cortex-M7
Expand All @@ -53,7 +53,7 @@
#endif

#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT != CONFIG_CPU_HAS_ICACHE)
#error "__ICACHE_PRESENT and CONFIG_CPU_HAS_ICACHE are not set to the same value"

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modules/cmsis_6/cmsis_core_m.h:56 
-#if  defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT != CONFIG_CPU_HAS_ICACHE)
+#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT != CONFIG_CPU_HAS_ICACHE)
#endif

#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT != CONFIG_CPU_HAS_DCACHE)
Expand All @@ -68,4 +68,4 @@
#error "__SAUREGION_PRESENT and CONFIG_CPU_HAS_ARM_SAU are not set to the same value"
#endif

#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_M_H_ */
#endif /* ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_H_ */
8 changes: 4 additions & 4 deletions modules/cmsis/cmsis_core_m_defaults.h → modules/cmsis_6/cmsis_core_m_defaults.h
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@@ -1,6 +1,6 @@
/*
* Copyright (c) 2017 Nordic Semiconductor ASA
* Copyright (c) 2023 Arm Limited
* Copyright 2023,2025 Arm Limited and/or its affiliates <[email protected]>
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand All @@ -13,8 +13,8 @@
* ARM CMSIS Core headers.
*/

#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_
#define ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_
#ifndef ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_
#define ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_

#include <zephyr/arch/arm/cortex_m/nvic.h>

Expand Down Expand Up @@ -113,7 +113,7 @@
#ifndef __PMU_PRESENT
#define __PMU_PRESENT CONFIG_ARMV8_1_M_PMU
#define __PMU_NUM_EVENTCNT CONFIG_ARMV8_1_M_PMU_EVENTCNT
#endif

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modules/cmsis_6/cmsis_core_m_defaults.h:116 
-	Reset_IRQn                    = -15,
-	NonMaskableInt_IRQn           = -14,
-	HardFault_IRQn                = -13,
+	Reset_IRQn = -15,
+	NonMaskableInt_IRQn = -14,
+	HardFault_IRQn = -13,
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	MemoryManagement_IRQn         = -12,
-	BusFault_IRQn                 = -11,
-	UsageFault_IRQn               = -10,
+	MemoryManagement_IRQn = -12,
+	BusFault_IRQn = -11,
+	UsageFault_IRQn = -10,
 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
-	SecureFault_IRQn              = -9,
+	SecureFault_IRQn = -9,
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
 #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
-	SVCall_IRQn                   =  -5,
-	DebugMonitor_IRQn             =  -4,
-	PendSV_IRQn                   =  -2,
-	SysTick_IRQn                  =  -1,
-	Max_IRQn                      =  CONFIG_NUM_IRQS,
+	SVCall_IRQn = -5,
+	DebugMonitor_IRQn = -4,
+	PendSV_IRQn = -2,
+	SysTick_IRQn = -1,
+	Max_IRQn = CONFIG_NUM_IRQS,
 } IRQn_Type;
 
 #if defined(CONFIG_CPU_CORTEX_M0)
-#define __CM0_REV        0
+#define __CM0_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M0PLUS)
-#define __CM0PLUS_REV    0
+#define __CM0PLUS_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M1)
-#define __CM1_REV        0
+#define __CM1_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M3)
-#define __CM3_REV        0
+#define __CM3_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M4)
-#define __CM4_REV        0
+#define __CM4_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M7)
-#define __CM7_REV        0
+#define __CM7_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M23)
-#define __CM23_REV       0
+#define __CM23_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M33)
-#define __CM33_REV       0
+#define __CM33_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M55)
-#define __CM55_REV       0
+#define __CM55_REV 0
 #elif defined(CONFIG_CPU_CORTEX_M85)
-#define __CM85_REV       0
+#define __CM85_REV 0
 #else
 #error "Unknown Cortex-M device"
 #endif
 
-#define __NVIC_PRIO_BITS               NUM_IRQ_PRIO_BITS
-#define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
-#endif /* __NVIC_PRIO_BITS */
+#define __NVIC_PRIO_BITS       NUM_IRQ_PRIO_BITS
+#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
+#endif                           /* __NVIC_PRIO_BITS */
 
 #ifndef __MPU_PRESENT
-#define __MPU_PRESENT             CONFIG_CPU_HAS_ARM_MPU
+#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
 #endif
 
 #ifndef __FPU_PRESENT
-#define __FPU_PRESENT             CONFIG_CPU_HAS_FPU
+#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
 #endif
 
 #ifndef __FPU_DP
-#define __FPU_DP                  CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
+#define __FPU_DP CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
 #endif
 
 #ifndef __VTOR_PRESENT
-#define __VTOR_PRESENT            CONFIG_CPU_CORTEX_M_HAS_VTOR
+#define __VTOR_PRESENT CONFIG_CPU_CORTEX_M_HAS_VTOR
 #endif
 
 #ifndef __DSP_PRESENT
-#define __DSP_PRESENT             CONFIG_ARMV8_M_DSP
+#define __DSP_PRESENT CONFIG_ARMV8_M_DSP
 #endif
 
 #ifndef __ICACHE_PRESENT
-#define __ICACHE_PRESENT          CONFIG_CPU_HAS_ICACHE
+#define __ICACHE_PRESENT CONFIG_CPU_HAS_ICACHE
 #endif
 
 #ifndef __DCACHE_PRESENT
-#define __DCACHE_PRESENT          CONFIG_CPU_HAS_DCACHE
+#define __DCACHE_PRESENT CONFIG_CPU_HAS_DCACHE
 #endif
 
 #ifndef __MVE_PRESENT
-#define __MVE_PRESENT             CONFIG_ARMV8_1_M_MVEI
+#define __MVE_PRESENT CONFIG_ARMV8_1_M_MVEI
 #endif
 
 #ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       CONFIG_CPU_HAS_ARM_SAU
+#define __SAUREGION_PRESENT CONFIG_CPU_HAS_ARM_SAU
 #endif
 
 #ifndef __PMU_PRESENT
-#define __PMU_PRESENT             CONFIG_ARMV8_1_M_PMU
-#define __PMU_NUM_EVENTCNT        CONFIG_ARMV8_1_M_PMU_EVENTCNT
+#define __PMU_PRESENT      CONFIG_ARMV8_1_M_PMU
+#define __PMU_NUM_EVENTCNT CONFIG_ARMV8_1_M_PMU_EVENTCNT

#ifdef __cplusplus
}
Expand Down Expand Up @@ -143,4 +143,4 @@
#error "Unknown Cortex-M device"
#endif

#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_ */
#endif /* ZEPHYR_MODULES_CMSIS_6_CMSIS_CORE_M_DEFAULTS_H_ */
2 changes: 1 addition & 1 deletion modules/trusted-firmware-m/CMakeLists.txt
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Expand Up @@ -289,7 +289,7 @@ if (CONFIG_BUILD_WITH_TFM)
${TFM_CMAKE_ARGS}
$<GENEX_EVAL:$<TARGET_PROPERTY:zephyr_property_target,TFM_CMAKE_OPTIONS>>
-DMBEDCRYPTO_PATH=$<IF:$<BOOL:$<TARGET_PROPERTY:zephyr_property_target,TFM_MBEDCRYPTO_PATH>>,$<TARGET_PROPERTY:zephyr_property_target,TFM_MBEDCRYPTO_PATH>,${ZEPHYR_MBEDTLS_MODULE_DIR}>
-DCMSIS_PATH=${ZEPHYR_TRUSTED_FIRMWARE_M_MODULE_DIR}/platform/ext/cmsis
-DCMSIS_PATH=${ZEPHYR_CMSIS_6_MODULE_DIR}
${ZEPHYR_TRUSTED_FIRMWARE_M_MODULE_DIR}
WORKING_DIRECTORY ${TFM_BINARY_DIR}
COMMAND_EXPAND_LISTS
Expand Down
8 changes: 5 additions & 3 deletions west.yml
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Expand Up @@ -129,8 +129,10 @@ manifest:
path: modules/lib/cmsis-nn
- name: cmsis_6
repo-path: CMSIS_6
revision: 783317a3072554acbac86cca2ff24928cbf98d30
path: modules/lib/cmsis_6
revision: 6dd50439a9b83398ff2ae1376eef0a2a0b95913b
path: modules/hal/cmsis_6
groups:
- hal
- name: edtt
revision: b9ca3c7030518f07b7937dacf970d37a47865a76
path: tools/edtt
Expand Down Expand Up @@ -358,7 +360,7 @@ manifest:
groups:
- tee
- name: trusted-firmware-m
revision: e2288c13ee0abc16163186523897e7910b03dd31
revision: 64738996dca5f5e058e0a358b81033f4b792be27
path: modules/tee/tf-m/trusted-firmware-m
groups:
- tee
Expand Down
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