Add DISCO_G474E_DPOW1 #1010

ErikIOT · 2020-03-25T03:11:48Z

https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html

ABOSTM

Hi @ErikIOT ,
Thanks for this PullRequest.
You cannot just copy what has been done on NUCLEO_G474RE (see my inline comments)
If needed you can look at https://github.com/stm32duino/wiki/wiki/Add-a-new-variant-%28board%29
to help you.

Also, Continuous Integration reports Astyle issue, can you run it :
https://github.com/stm32duino/wiki/wiki/Astyle

Thanks

ABOSTM · 2020-03-25T10:33:05Z

variants/DISCO_G474E_DPOW1/PeripheralPins.c

+  // {PA_2,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+  // {PA_2,  TIM15,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1
+  // {PA_3,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+  /// {PA_3,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4


Typo:

Suggested change

/// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4

// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4

ABOSTM · 2020-03-25T10:34:19Z

variants/DISCO_G474E_DPOW1/PeripheralPins.c

+
+#ifdef HAL_CAN_MODULE_ENABLED
+WEAK const PinMap PinMap_CAN_RD[] = {
+  {PA_8,  CANFD3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_FDCAN3)},


For this STM32 family CAN peripheral are named FDCANx (and not CANFDx).
More generally the PeripheralPin.c must be based on generated file available here: https://github.com/stm32duino/Arduino_Tools/blob/master/src/genpinmap/Arduino/STM32G4/STM32G474R(B-C-E)Tx/PeripheralPins.c
So can you rework, base on this file ?

ABOSTM · 2020-03-25T10:39:50Z

variants/DISCO_G474E_DPOW1/ldscript.ld

+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for NUCLEO-G474RE Board embedding STM32G474RETx Device from STM32G4 series


Suggested change

** Abstract : Linker script for NUCLEO-G474RE Board embedding STM32G474RETx Device from STM32G4 series

** Abstract : Linker script for B-G474E-DPOW1

Board embedding STM32G474RETx Device from STM32G4 series

ABOSTM · 2020-03-25T10:49:04Z

keywords.txt

+JOY_LEFT	LITERAL1
+JOY_DOWN	LITERAL1
+JOY_RIGHT	LITERAL1
+JOY_UP	LITERAL1


wrong tabulation

https://arduino.github.io/arduino-cli/library-specification/#keywordstxt-format

keywords.txt is formatted in four fields which are separated by a single true tab (not spaces)

So it can appears not aligned.

ABOSTM · 2020-03-25T10:52:36Z

variants/DISCO_G474E_DPOW1/variant.h

+// CN9
+#define PC5  0
+#define PC4  1
+#define PA10 2
+#define PB3  3
+#define PB5  4
+#define PB4  5
+#define PB10 6
+#define PA8  7
+// CN5
+#define PA9  8
+#define PC7  9
+#define PB6  10
+#define PA7  11
+#define PA6  12
+#define PA5  13 // LED
+#define PB9  14
+#define PB8  15
+// CN7 Left Side
+#define PC10 16
+#define PC12 17
+#define PA13 18 // SWDIO
+#define PA14 19 // SWCLK
+#define PA15 20
+#define PB7  21
+#define PC13 22
+#define PC14 23
+#define PC15 24
+#define PF0  25
+#define PF1  26
+#define PC2  27
+#define PC3  28
+// CN7 Right Side
+#define PD2  29
+#define PC11 30
+// CN10 Left Side
+#define PC9  31
+// CN8
+#define PA0  32 // A0
+#define PA1  33 // A1
+#define PA4  34 // A2
+#define PB0  35 // A3
+#define PC1  36 // A4
+#define PC0  37 // A5
+// CN10 Right side
+#define PB13 38 // A6
+#define PB14 39 // A7
+#define PB15 40 // A8
+#define PB1  41 // A9
+#define PB2  42 // A10
+#define PB11 43 // A11
+#define PB12 44 // A12
+#define PA11 45
+#define PA12 46
+#define PC6  47
+#define PC8  48
+#define PA2  49
+#define PA3  50


I don't know where those definition comes from, but It looks like the whole PIN definition is wrong:
PC4, PC5 are on CN8 not CN9
All pins are concentrated on CN8 and CN9, there is no MCU pin on CN7.
...
It needs to be fully reworked.

ABOSTM · 2020-03-25T10:56:54Z

variants/DISCO_G474E_DPOW1/variant.cpp

+  PC_5,  //D0
+  PC_4,  //D1
+  PA_10, //D2
+  PB_3,  //D3
+  PB_5,  //D4
+  PB_4,  //D5
+  PB_10, //D6
+  PA_8,  //D7
+  // CN5
+  PA_9,  //D8
+  PC_7,  //D9
+  PB_6,  //D10
+  PA_7,  //D11
+  PA_6,  //D12
+  PA_5,  //D13/LED
+  PB_9,  //D14
+  PB_8,  //D15
+  // CN7 Left Side
+  PC_10, //D16
+  PC_12, //D17
+  PA_13, //D18/SWDIO
+  PA_14, //D19/SWCLK
+  PA_15, //D20
+  PB_7,  //D21
+  PC_13, //D22
+  PC_14, //D23
+  PC_15, //D24
+  PF_0,  //D25
+  PF_1,  //D26
+  PC_2,  //D27
+  PC_3,  //D28
+  // CN7 Right Side
+  PD_2,  //D29
+  PC_11, //D30
+  // CN10 Left Side
+  PC_9,  //D31
+  // CN8
+  PA_0,  //D32/A0
+  PA_1,  //D33/A1
+  PA_4,  //D34/A2
+  PB_0,  //D35/A3
+  PC_1,  //D36/A4
+  PC_0,  //D37/A5
+  // CN10 Right side
+  PB_13, //D38/A6
+  PB_14, //D39/A7
+  PB_15, //D40/A8
+  PB_1,  //D41/A9
+  PB_2,  //D42/A10
+  PB_11, //D43/A11
+  PB_12, //D44/A12
+  PA_11, //D45
+  PA_12, //D46
+  PC_6,  //D47
+  PC_8,  //D48
+  PA_2,  //D49
+  PA_3   //D50


Same remark than variant.h, it doesn't match CNx connectors

ABOSTM · 2020-03-25T11:13:36Z

variants/DISCO_G474E_DPOW1/variant.h

+#define TIMER_SERVO             TIM7
+
+// UART Definitions
+#define SERIAL_UART_INSTANCE    0 //Connected to ST-Link


USART3 is connected to STlink

ABOSTM · 2020-03-25T11:14:23Z

variants/DISCO_G474E_DPOW1/variant.h

+#define PIN_SERIAL_RX           PA3
+#define PIN_SERIAL_TX           PA2


PC11 and PC10 are connected to STlink RX and TX

ABOSTM · 2020-03-25T11:26:45Z

boards.txt


+# DISCO_B-G474E-DPOW1 board
+Disco.menu.pnum.DISCO_B-G474E-DPOW1=DISCO_G474E_DPOW1
+Disco.menu.pnum.DISCO_B-G474E-DPOW1.node="No_mass_storage_for_this_board_Use_STLink_upload_method"


.node is the name of the computer mounted disk when you plug STlink USB cable to your computer.
I think this board support Mass Storage. But I don't have a board with me to verify, Chan you check this ?

fpistm · 2020-03-25T16:25:21Z

It seems the variant.h and ldscript.ld has been pushed with CRLF line endings.
Could you change it to LF line endings, it should be automatically converted to LF when you commit thanks the .gitattributes but I suspect you have some gitconfig option which override the repo config.

Thanks in advance.

fpistm · 2020-04-20T13:11:59Z

Any update on this?

fpistm · 2020-04-29T12:37:18Z

Nu user feedback since it was created --> closed

ErikIOT added 3 commits March 24, 2020 22:57

Add files via upload

781eab7

Update boards.txt

6c1de78

Update keywords.txt

05956d8

fpistm requested a review from ABOSTM March 25, 2020 08:58

fpistm added the new variant Add support of new bard label Mar 25, 2020

ABOSTM suggested changes Mar 25, 2020

View reviewed changes

fpistm added the waiting feedback Further information is required label Apr 20, 2020

fpistm closed this Apr 29, 2020

fpistm added abandoned No more work on this and removed waiting feedback Further information is required labels Apr 29, 2020

	/// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
	// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4

Add DISCO_G474E_DPOW1 #1010

Add DISCO_G474E_DPOW1 #1010

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ErikIOT commented Mar 25, 2020 • edited by fpistm Loading Uh oh! There was an error while loading. Please reload this page.

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ABOSTM Mar 25, 2020 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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fpistm commented Mar 25, 2020

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ErikIOT commented Mar 25, 2020 •

edited by fpistm

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ABOSTM Mar 25, 2020 •

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