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Yosys upgrade WIP PR #2 for testing #3093

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loglav03
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Description

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@github-actions github-actions bot added lang-cpp C/C++ code lang-python Python code lang-make CMake/Make code lang-hdl Hardware Description Language (Verilog/VHDL) lang-shell Shell scripts (bash etc.) Parmys labels May 28, 2025
@loglav03
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loglav03 commented Jun 4, 2025

@vaughnbetz -- Hi Vaughn, not sure if you saw my email with the QoR comparison tables, so I added you here with the tables attached for review. I wanted to check if the results of these QoR are okay to update the golden results.

vtr_strong_soft_multipliers_compare.xlsx
vtr_strong_global_nonuniform_compare.xlsx
vtr_strong_cin_tie_off_compare.xlsx
vtr_reg_basic_no_timing_compare.xlsx
nightly_test3_reg_qor_chain_compare.xlsx

@AlexandreSinger
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@vaughnbetz
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The QoR comparisons you posted all look good @loglav03 . Synthesis time is down significantly. On the only test listed with significant size circuits (nightly_test3_reg_qor_chain, which uses the VTR designs) parmys time is down by 33%, ab_synth time is down by 11%, and total flow l runtime is down 7%. pre-packed blocks and post-packed blocks are essentially unchanged, as are CLB count, RAM count and multiplier count, and the final critical path delay and wirelength are changed small amounts and for the better (0.4% less wirelength, .1% critical path delay reduction -- note that the best numbers from these come from "crit_path_routed_wirelength and "critical_path_delay" which use a channel width of 1.3 * Wmin). Individual circuits also look OK from the VTR design suite.

The other smaller circuits tests also all look good.

Go ahead and update any golden results necessary.

The only remaining thing that would be good to see is a QoR comparison on Koios. I'm confident it will be fine given these results, but it's still better to be safe. Please link a spreadsheet here.

In this PR's description it would be good to say what version of yosys or what date of yosys code you are updating to, so we can refer back to it here if needed in the future.

After that, this should be fine to check in.

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