OCTAL BUS TRANSCEIVER DESCRIPTION The TS4LS245/T74LS245 is an Octal Bus Transcei- ver intended for 8-line asynchronous 2-way data communication between data buses. Direction In- put (DR) takes over the transmission of Data from bus A to bus 8 or bus B to bus A depending on its logic level. Enable input is usable for isolation of the buses. # 2-WAY ASYNCHRONOUS DATA BUS COMUNICATION © HYSTERESIS INPUTS TO IMPROVE NOISE IMMUNITY © INPUT DIODES LIMIT HIGH-SPEED TERMINATION EFFECTS. TRUTH TABLE INPUTS 5 OUTPUT E oR L L Bus 8 Data to Bus A L H Bus A Data to Bus B H x Isolation cy DiD2 Plastic Package Coramic Package — we mt ct Micro Package Plastic Chip Carrier ORDERING NUMBERS: Ts4Ls245 D2 Tr4Lse24s C1 TraLs24s 01 T74LS245 Mt TraLs24s B1 PIN CONNECTION (top view) DUAL IN LINE H=HIGH Voltage Level L=LOW Voltage Level X= Don't Care NC=No Internal Connection 379 4187ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Voc. Supply Voltage =05 to7 Vv vi Input Voltage, Applied to Input =05 10 15 Vv Vo Output Voltage, Applied to Output Oto 10 Vv i Input Current, Into Inputs =30 to § mA To ‘Output Current, into Outputs 50 mA Stresses in excess of those listed under This is a stress rating only and functional indicated in the operational sections of this “Absolute Maximum Ratings” may cause permanent damage to the device. operation of the device at these or any other conditions in excess of those ‘specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabil lity GUARANTEED OPERATING RANGES | ‘Supply Voltage Pi atu art Numbers Min ie ax Temperature ‘TSaLs24502 (easy! 50V 55 V 35°C to + 125°6 T7ALS245XX 475 V BOV sasv | O° to + 70°C XX= package type. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE Limits = Symbol Parameter 7 ene Units Min. | Typ. | Max. (Note 1) Vin Input HIGH Voltage 20 Guaranteed input HIGH Voltage v for all Inputs Vit Input LOW Voltage [54 0.7 _| Guaranteed input LOW Voltage 74 8 | for all inputs . Vra-Vr_| Hysteresis o2 | 04 Voo=MIN v Veo __| input Clamp Diode Voltage =0.65| 1.5 | Voc=MINly= ~18mA v Von | Output HIGH Voltage [54,74 | 24 | a4 Voo=MIN, low = ~3.0mA 5474 | 20 Ton = = ¥2mA for 54LS. v lon=—15mA for 7aLs_| Yoo= MIN Vou Output LOW Voltage [54,74 0.25 | 04 | tov=t2mA [Vog=MIN, Viy= Vi or 74 0.38 | 0.5 | Iou=24ma | Vin per Truth Table ue loze __| Output Off Current HIGH 20_| Voo=MAX. Vour=2.7V oA lozi__| Output Off Current Low 200 | Voo=MAX, Vour=0.4V oA ta Input HIGH Current_ Aor B, OR or E 20 1AXViy = 2.7V WA DR or o4 1AX,Viy = 7.0V mA AorB 0.1 | Voc=MAX. Vin=5.5V mA ie Input LOW Current =0.2 | Voc =MAX.Viy=0.4V mA los Output Short Circuit Current_ | 40 = 225 | Voc = MAX (Note 2) mA lee Power Supply Current Total, Output HIGH 70 | Voc=MAX mA Total, Output LOW 80 Total at HIGH Z 95 Note 1) For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2) Not more than one output should be shorted at a time. 3) Typical values are at Vog=5.0V. Ty =25°C 380AC CHARACTERISTICS: T, =25°C Limits Symbol Parameter = Test Conditions Units in. ten | Propagation Delay, ns tont___| Data to Output tezu __| Output Enable Time 25 | 40 | C.=45pF ns 10 HIGH Level Ry, =6670 tez. | Output Enable Time a | 40 ns to LOW Level tez __| Output Disable Time 15 | 25 ns {rom LOW Level 15.09 tenz | Output Disable Time 16 | 25 ns from HIGH Level 38114-LEAD PLASTIC DIP 14-LEAD CERAMIC DIP. ay ‘sm 3 025, 952001 16-LEAD PLASTIC DIP al 93816-LEAD CERAMIC DIP fos Rs nT 1178 annaonoadgl crore 20-LEAD PLASTIC DIP zat & oar ee ro) | “sf 025. wall Emcee | as 25.09" 20-LEAD CERAMIC DIP _ 1am} e 2) aloe Feet 25m hoononoded error 0607 A-14 -24-LEAD PLASTIC DIP wom a. 18208 22 24-LEAD CERAMIC DIP 0608 B-01 oe14-LEAD PLASTIC DIP MICROPACKAGE 16-LEAD PLASTIC DIP MICROPACKAGE oxe__asve wn Ene BS - eee a | ee i 14 NOTE: FOR 20-LEAD PLASTIC DIP MICROPACKAGE CONTACT SGS‘One possible solution to the important problem of PWB minimization, is that of using surface mounted components. Integrated circuits in SO (Small Outline) packages are made up of standard chips mounted in very small plastic packages. ‘The advantages given by using these devices are: PWB Reduction This Is by far the most important advantage since the reduction of PWB size varies from 40 to 60% in comparison with standard board types. (See page 584 for package dimensions.) Assembly Cost Reduction SO Devices require no preliminary operation prior to mounting and can therefore be easily utilized in fully automatic equipment, Increasing Reliability ‘The following characteristics lead to a higher level of reliability with respect to their standard packag- ed counter paris: - The mounting system is fully automatic ~ PWB number and the interconnections between them are reduced when the same number of devices are used. ~The high density of components on the board makes it thermally much more stable. Noise Reduction and Improved Frequency Response The reduction of the length of the connecting wires between the leads and the silicon guarantees a more homogeneous propogation delay between the external pins, with respect to the standard type. Assembly Without Board Holes The devices are placed on the board and soldered. This technology permits a higher level of tolerance in the positioning (automatic) of the device. For the standard DIP types this must be done with great accuracy due to the insertion of the leads into their holes. ENCAPSULATION