SystemC-TLM
Transaction Level Modeling
Alexander de Graaf, EEMCS-CAS
17-5-2011
Delft
University of
Technology
Challenge the future
1.
SystemC-TLM
Transaction Level Modeling
SystemC-TLM
Topics
Simulation Use Cases
Basic Concepts
Generic Payload Information
API The Transaction Call
Sockets Connectivity
Loosely Timed Fast
Approximately Timed Accurate
Base Protocol Modeling
abstraction
An example
SystemC-TLM
Simulation Use Cases
Architectural Analysis
Do interconnections meet
needs?
Requires quick modeling and
1st order accuracy
Hardware Development
Early development
Improve schedule and
ensure sufficient coverage
Requires some accuracy
Software Development
Early development
Requires speed
Architectural Analysis
Do interconnections meet
needs?
Requires quick modeling and
1st order accuracy
SystemC-TLM
Fundamental Ideas
TLM 2.0 models Memory-Mapped Bus-Transport
Exchange information (payload)
between initiator and target
Initiator
Initiator
Initiator
Target
Target
Target
time
Information
Updated
SystemC-TLM
Four Basic TLM 2.0 Concepts
1. Core interfaces
my_skt->b_transport(gp, )
2. Sockets & Connectivity
Initiator
Initiator
2. Generic payload
Command
Address
Data
Byte enables
Response status
Extensions
Target
Target
&
payload
reference
4. Base protocol
BEGIN_REQ
END_REQ
BEGIN_RESP
END_RESP
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Many Configurations Considered
MPU
MPU
CPU
CPU
I/O
I/O
Interconnect
Interconnect
Mem
Mem
CPU
CPU
Mem
Mem
Processor
Processor bus
bus
I/O
I/O
DMA
DMA
Peripheral
Peripheral bus
bus
Mem
Mem
Periph
Periph
SystemC-TLM
Arbiter
Arbiter
Core Interface The Transaction Call
Generally one of two simple transport calls
1. void
void
b_transport(TRANS& payload, sc_time& t);
2. void
void
nb_transport_fw(TRANS& payload,
PHASE& ph,
sc_time& t);
Declared beneath interface classes ( enables port/socket)
tlm::tlm_fw_transport_if<>
tlm::tlm_bw_transport_if<>
Implemented as methods (member function) of models
TLM models are disguised SystemC channels
SystemC-TLM
Generic Payload - Information
What is the Payload?
Simple structured object that contains:
Control (command)
Data
Various Properties & Extensions
Designed for memory mapped buses
Burst size
Byte lanes
Defined as a class for flexibility
Payload is passed by reference
Speeds calling by reducing copy overhead
Need to be cognizant of lifetime
SystemC-TLM
Simple Transport Call
sc_time
tDelay;
tlm::tlm_generic_payload payload;
sc_core::uint32
addr(55);
payload.set_address(addr);
payload.set_data_ptr(&data);
payload.set_write(); // command
tDelay = SC_ZERO_TIME;
// Execute a transaction
b_transport(payload, tDelay);
wait(tDelay);
SystemC-TLM
10
TLM Sockets - more than convenient
Transactions include communications in both directions
Initiator to target
Target to initiator
Normally requires port/export and export/port pair
(i.e. a lot of binding)
Initiator
Initiator
Target
Target
Replaced with specialized port
(simplifies binding)
Initiator
Initiator
Target
Target
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11
TLM 2.0 Socket Graphically
Initiator_mdl
Initiator_mdl
Target_mdl
Target_mdl
init_process
init_skt->fw()
Foreward
methods
Backward
methods
init_skt->bw()
target_process
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12
Example: Initiator declaration
class Initiator_mdl
: public sc_module, public tlm_bw_transport_if<>
{
public:
tlm::tlm_initiator_socket<> init_socket;
SC_TOR(Initiator_mdl); // Constructor
~Initiator_mdl();
// Destructor
void init_process();
// forward call made here
};
// Backwards flowing API for initiator socket
// Must implement all backward calls ( even if trivially)
tlm::tlm_sync_enum nb_transport_bw( );
void invalidate_direct_mem_ptr ( );
SystemC-TLM
13
Example: Target declaration
class Target_mdl
: public sc_module, public tlm_fw_transport_if<>
{
public:
tlm::tlm_target_socket<> targ_skt;
SC_TOR(Target_mdl); // Constructor
~Target_mdl();
// Destructor
};
// Forwards flowing API for initiator socket
// Must implement all forward calls ( even if trivially)
void
b_transport ( );
tlm::tlm_sync_enum nb_transport_fw( );
void
get_direct_mem_ptr ( );
void
transport_dbg ( );
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14
Example: Top-level connectivity
class Top_mdl : public sc_module
{
public:
Initiator_mdl *init_ptr;
Target_mdl *targ_ptr;
SC_TOR(Top_mdl) {
new Initiator_mdl(init);
new Target_mdl(targ);
init_ptr->init_skt.bind( targ_ptr->targ_skt );
}
};
~Top_mdl();
// Destructor
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Model Coding Styles
TLM 2.0 introduces two terms
Loosely Timed (LT) modeling fast
approximately Timed (AT) modeling accurate
Terminology that roughly defines
Simulation speed
Timing accuracy
Model applicability
Older terminology
Untimed(UT), Programmers View (PV),
Programmers View with Timing (PVT), Cycle Accurate
Too specific and often miss the point
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Loosely Timed (LT) - fast
Use Case
Early Software Development
Hardware Verification of portions of functionality
Speed up portions of other use cases prior to analysis
Characteristics
Just enough detail to boot O/S and run multicore-systems
Processes can run ahead of simulation time (temporal decoupling)
Transactions have two timing points: begin and end
Maybe easier to code due to less detail
template<class PAYLD = tlm_generic_payload >
class tlm_blocking_transport_if : sc_interface {
virtual void b_transport( PAYLD& , sc_time&) = 0;
};
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Loosely Timed Mechanisms
Impediments to speed
Context switching
wait()
next_trigger(); return;
Doesnt matter whether SC_THREAD or SC_METHOD
Complex bus protocols and lots of processes
Reduce context switching to improve simulation speed
Temporal decoupling
When time doesnt matter as much
Keep track of local time
Direct Memory Interface
Bypass bus for some purposes to gain performance
SystemC-TLM
18
Blocking Transport/ LT Modeling (1/2)
Target
Initiator
tsim = 100ns
Call
b_transport(gp, 0ns)
Initiator is blocked until return from b_transport
tsim = 140ns
tsim = 140ns
b_transport(gp, 0ns)
Call
Return
b_transport(gp, 0ns)
Initiator is blocked until return from b_transport
tsim = 180ns
wait(40ns)
b_transport(gp, 0ns)
wait(40ns)
Return
Not Optimal
SystemC-TLM
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19
Blocking Transport/ LT Modeling (2/2)
Target
Initiator
tsim = 180ns
Call
tlo
tsim = 180ns
b_transport(gp, 0ns)
b_transport(gp, 40ns)
cal
Return
= 18
0+40
ns
Call
b_transport(gp, 40ns)
tlo
b_transport(gp, 80ns)
cal
= 18
0+80
ns
tlo
cal
= 26
0+0
ns
Return
wait(80ns)
tsim = 260ns
Fewer context switches = faster simulation
SystemC-TLM
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20
Approximately Timed - Accurate
Use cases
Architectural Analysis, Software Performance Analysis
Hardware Verification
Characteristics
Sufficient for architectural and performance exploration
Processes run in lock-step with simulation time
Transactions have four timing points
template<typename PAYLD = tlm_generic_payload,
typename PHASE = tlm_phase >
class tlm_nonblocking_transport_if : sc_interface {
virtual void nb_transport_fw( PAYLD& , PHASE&, sc_time&) = 0;
};
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Approximately Timed Mechanisms
Concerns Providing sufficient accuracy
Negotiation time
Command (read/write) execution time
Response time
Simulation time fidelity
Bus interactions
Techniques
Base Protocol with four timing points
Non-blocking calls (slight coding complexity)
Payload Event Queue to model transport delay
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Non-Blocking/ AT Modeling continued
Also has backward initiated component
template<typename PAYLD = tlm_generic_payload,
typename PHASE = tlm_phase >
class tlm_bw_nonblocking_transport_if : sc_interface {
virtual void nb_transport_bw( PAYLD& , PHASE&, sc_time&) = 0;
};
Initiator
Initiator
Forward
path
Target
Target
Backward
path
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Four Timing Points = Four Phases
BEGIN_REQ (Begin Request)
Initiator acquires bus
Connections becomes busy and blocks further requests
Payload becomes busy
END_REQ
Target accepts request and completes the handshake
Bus freed to start additional requests
BEGIN_RESP
Target acquires bus to provide a response
Bus becomes busy
END_RESP
Initiator acknowledges response to complete it
Bus freed
Payload reference freed up
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Non-Blocking Return Type
TLM_ACCEPTED
Transaction, phase and timing arguments unmodified (ignored) on return
Target may respond later (depending on protocol)
TLM_UPDATED
Transaction, phase and timing arguments updated (used) on return
Target has advanced the protocol state machine to the next state
TLM_COMPLETED
Transaction, phase and timing arguments updated (used) on return
Target has advanced the protocol state machine straight to the final phase
enum tlm_sync_enum
{ TLM_ACCEPTED, TLM_UPDATED, TLM_COMPLETED };
SystemC-TLM
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Base Protocol and AT
TLM 2.0 defines Base Protocol
High-level concept modeling time progression
Maps to many bus protocols in a rough manner
a single TLM transaction may cross one or more busses
Possibly each with a different hardware protocol
Following slides illustrate some of the TLM possibilities
4 distinct phases using the backward path
2 distinct phases using the return path
1 combined phase with early return completion
Use of timing annotation possible as well
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Notation for Message Sequence Charts
Simulation time = 5us
Local time
+10ns
= sc_time_stamp()
For temporal decoupling, local time is added to
simulation time (explained on slides)
+20ns
status = nb_transport ( trans, phase, delay ) ;
Call
-, BEGIN_REQ, 0ns
Return
TLM_COMPLETED, BEGIN_RESP, 10ns
Arguments passed to function
Values returned from function
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Using the Backward Path
Phase
Target
Initiator
Simulation time = 100ns
Call
BEGIN_REQ
Return
-, BEGIN_REQ, 0ns
TLM_ACCEPTED, -, -
Simulation time = 110ns
-, END_REQ, 0ns
END_REQ
Call
TLM_ACCEPTED, -, -
Return
-, BEGIN_RESP, 0ns
Call
TLM_ACCEPTED, -, -
Return
Simulation time = 120ns
BEGIN_RESP
Simulation time = 130ns
Call
END_RESP
Return
-, END_RESP, 0ns
TLM_ACCEPTED, -, -
Transaction accepted now, caller asked to wait
SystemC-TLM
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Using the Return Path
Phase
Target
Initiator
Simulation time = 100ns
Call
BEGIN_REQ
END_REQ
Return
-, BEGIN_REQ, 0ns
TLM_UPDATED, END_REQ, 10ns
Simulation time = 110ns
Simulation time = 150ns
-, BEGIN_RESP, 0ns
BEGIN_RESP
END_RESP
TLM_UPDATED, END_RESP, 5ns
Call
Return
Simulation time = 155ns
Callee annotates delay to next transition, caller waits
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Early Completion
Phase
Target
Initiator
Simulation time = 100ns
Call
BEGIN_REQ
END_RESP
-, BEGIN_REQ, 0ns
TLM_COMPLETED, -, 10ns
Return
Simulation time = 110ns
Callee annotates delay to next transition, caller waits
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Timing Annotation
Target
Initiator
Phase
Simulation time = 100ns
Call
-, BEGIN_REQ, 10ns
TLM_ACCEPTED, -, -
BEGIN_REQ
Return
Payload
Event
Queue
Simulation time = 110ns
Simulation time = 125ns
-, END_REQ, 10ns
Payload
Event
Queue
END_REQ
Return
Call
TLM_ACCEPTED, -, -
Simulation time = 135ns
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Summary: Key Features of TLM-2
Transport interfaces with timing annotation and phases
DMI and debug interfaces
Loosely-timed coding style and temporal decoupling for
simulation speed
Approximately-timed coding style for timing accuracy
Sockets for convenience and strong connection checking
Generic payload for memory-mapped bus modelling
Base protocol for interoperability between TL- models
Extensions for flexibility of modelling
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MBLite Platform
Router.map
MBLite ISS
router
1i
2i
1tMemory
Ni
2tUart
1i
1tTerminal
Nt
Wishbone bus
1i
2i
1t
1t
Slave1
Slave2
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