ECE 410: VLSI Design

Course Introduction

Professor Andrew Mason

Michigan State University
Spring 2008

ECE 410, Prof. A. Mason Lecture Notes Page i.1

 Electronics Revolution
• Age of electronics
– microcontrollers, DSPs,
and other VLSI chips are
everywhere

• Electronics of today
Digital Camera PDAs Camcorder
and tomorrow demand…
– higher performance
(speed) circuits
– low power circuits for
portable applications
– more mixed signal
emphasis
MP3/CD Player Laptop Cell phone
• wireless hardware
• high performance signal
processing Handheld
Games
• sensors and
& Video Players
microsystems
ECE 410, Prof. A. Mason Lecture Notes Page i.2
 VLSI Design Flow
VLSI = very large scale Top

integration
Down System Specifications
Design

– lots of transistors
Abstract High-level Model
VHDL, Verilog HDL

integrated on one chip

Logic Synthesis
Chip Development Cycle
Functional Simulation Chip Floorplanning

Digital Cell Chip-level Integration

Library

Design Methodologies Post-Layout Mixed-signal

Manufacturing
• Top Down Design Simulation Analog Blocks

– coded circuit functionality

VLSI Design
Parasitic Extraction

Procedure
for rapid design
ECE410 Finished VLSI Chip
LVS
– digital only (layout vs. schematic)

– covered in ECE 411 DRC Process

Process
Characterization
• Bottom Up Design (design rule check) Design Rules

Process
– transistor-level design Physical Design
Design
with focus on circuit Simulation
Process Models
performance SPICE

– digital & mixed signal Schematic Design

– covered in ECE 410 Bottom

Up Functional/Timing/ Process Capabilities
Design Performance Specifications and Requirements

ECE 410, Prof. A. Mason Lecture Notes Page i.3

 410 Course Objectives
• Understand and Experience VLSI Design Flow
• Learn Transistor-Level CMOS Logic Design
• Understand VLSI Fabrication and Experience CMOS
Physical Design
• Learn to Analyze Gate Function and Timing
Characteristics
• Study High-Level Digital Functional Blocks
• Visualize CMOS Digital Chip Design

ECE 410, Prof. A. Mason Lecture Notes Page i.4

 410 Syllabus
• Instructor: Dr. Andrew Mason, EB 1217, [email protected]
• Lecture: MWF, 11:30 12:20, 1145 Engineering Bldg
• Office Hrs.: Wed: 10-11:30, or send email for an appointment
• Lab: Labs are open; you will not be “attending” a lab at the lab time
you enrolled up for
• Lab TA/Instructor Email: [email protected]
This email alias for the instructor and TAs should be used for all
general lab/project questions so that the first person available can
answer your question.
• Lab/TA Hours:
You may work on your assignments in any available PC lab any time
you wish. TAs will be available to answer questions at designated
times that will be posted on the class website.
• Course Website: www.egr.msu.edu/classes/ece410/mason/
• Email: Please check/forward your EGR email

ECE 410, Prof. A. Mason Lecture Notes Page i.5

 410 Syllabus
• Textbook:
J. Uyemura, Introduction to VLSI Circuits and Systems, Wiley, 2002.
ISBN 0-471-12704-3
– textbook has good examples; some homework problems from textbook

• Attendance and Conduct in Class:

Students are expected to attend class and be bright and cheerful with lots
of questions. It will be difficult to perform well in this class without
attending the lectures. It is the student’s responsibility to get notes and
handouts for any missed class.
• Grading:
30% 2 Midterm Exams
15% Homework *
5% Participation (attendance, quizzes, etc.) *
25% Lab Assignments (Lab 1-7) *
25% Design Project (Labs 8-10, Proposal, Project Demo, Project Report)
* must obtain a grade of 60% or better to pass the course
Tentative dates for the two midterm exams are shown on the Course Topic
Outline (also posted on the web). There is no final exam, only a final design
project. Ten homework assignments will be due weekly before class on
Wednesdays. Approximately 10 5-minute quizzes will be given at the
beginning of class on random days.

ECE 410, Prof. A. Mason Lecture Notes Page i.6

 410 Lab Issues
• When can I work on lab assignments?
– open lab, work in any PC lab when you want
– TAs will be in lab at set times each week to assist you
• schedule will be posted on the class website
• Who is the TA?
– Zeyong Shan: lab hours & lab grader
• What’s the lab process?
– assigned each week on a Friday
– in-lab check off by the next Friday
• must show/demonstrate specific results to TA
– lab reports due in class on Monday
• see format/sample on the class website
• When will labs begin?
– first assignment next Friday –need to learn stuff in class first

ECE 410, Prof. A. Mason Lecture Notes Page i.7

 Integrated Circuit Technologies
• “Technologies” for digital ICs
– passive (inert) circuits:
• resistors and capacitors only, no transistors
– active circuits; with transistors
• III-V devices (compound semic.)
• MOS and Bipolar devices (silicon)
• ECE410 will cover CMOS because…
• CMOS dominates the semiconductor/IC industry
– Silicon is cheaper Î preferred over other materials
– physics of CMOS is easier to understand
– CMOS is easier to implement/fabricate
– CMOS provides lower power-delay product
– CMOS is lowest power
– density: can get more CMOS transistors/functions in same chip area
• BUT! CMOS is not the fastest technology!
– BJT and III-V devices are faster

ECE 410, Prof. A. Mason Lecture Notes Page i.8

 What is a MOSFET?
• Digital integrated circuits rely on transistor switches
– most common device for digital and mixed signal: MOSFET
• Definitions V
– MOS = Metal Oxide Semiconductor Metal gate
• physical layers of the device Oxide
insulator
E
– FET = Field Effect Transistor channel
source ------------ drain
• What field? What does the field do?
• Are other fields important? Semi-
silicon substrate
conductor
– CMOS = Complementary MOS
• use of both nMOS and pMOS to form a circuit
• Primary Features
– gate
– gate oxide (insulator) NOTE: “metal” is replaced by
– source and drain polysilicon in modern MOSFETs
– bulk/substrate
– channel
ECE 410, Prof. A. Mason Lecture Notes Page i.9
 MOSFET Physical View
• Physical Structure of a MOSFET Device

L = channel length
critical dimension = “feature size”

• Schematic Symbol for 4-terminal MOSFET

gate

source drain note: no physical

connection at Gate
Substrate, bulk, well, or back gate terminal, symbolic
of gate insulator in
• Simplified Symbols MOSFET

nMOS pMOS

ECE 410, Prof. A. Mason Lecture Notes Page i.10

 CMOS Cross Section View
• Cross section of a 2 metal, 1 poly CMOS process
Typical MOSFET Device (nMOS)

• Layout (top view) of the devices above (partial, simplified)

ECE 410, Prof. A. Mason Lecture Notes Page i.11

 Fundamental Relations in MOSFET
• Electric Fields V
gate
– fundamental equation
E insulator
• electric field: E = V/d
channel
– vertical field through gate oxide source - - - - - - - - - - drain
• determines charge induced in channel - -silicon substrate
– horizontal field across channel
• determines source-to-drain current flow
• Capacitance
– fundamental equations Q+ +
• capacitor charge: Q = CV C Q-
V
• capacitance: C = ε A/d -
– charge balance on capacitor, Q+ = Q-
• charge on gate is balanced by charge in channel
• what is the source of channel charge? where does it come from?

ECE 410, Prof. A. Mason Lecture Notes Page i.12

 CMOS Technology Trends
• Variations over time
– # transistors / chip: increasing with time
– power / transistor: decreasing with time (constant power density)
– device channel length: decreasing with time
– power supply voltage: decreasing with time

transistors /
chip channel length

power /
transistor supply voltage

rref: Kuo and Lou, Low-Voltage CMOS VLSI Circuits, Fig. 1.3, p. 3

low power/voltage is critical for future ICs

ECE 410, Prof. A. Mason Lecture Notes Page i.13
 Moore’s Law
•In 1965, Gordon Moore realized there was a striking trend; each new
generation of memory chip contained roughly twice as much capacity as its
predecessor, and each chip was released within 18-24 months of the
previous chip. He reasoned, computing power would rise exponentially over
relatively brief periods of time.

•Moore's observation, now known as Moore's Law, described a trend that has
continued and is still remarkably accurate. In 26 years the number of
transistors on a chip has increased more than 3,200 times, from 2,300 on
the 4004 in 1971 to 7.5 million on the Pentium¨ II processor in 1998.

10μm 1μm 0.35μm

Feature Size
(ref: http://www.intel.com/intel/museum/25anniv/hof/moore.htm)

ECE 410, Prof. A. Mason Lecture Notes Page i.14

 GSM Digital Baseband Evolution

Year 1994 1997 1999 2000 2002 2004 2006 2008

Nano-
meter 500nm 350nm 250nm 180nm 130nm 90nm 65nm 45nm
Wafer
size 6" 8" 8" 8" 12" 12" 12" 12"
Die size
(mm2) 80.7 46.6 19.2 10.7 6.7 4.2 2.4 1.4
Dies per
wafer 310 950 2550 4700 12,200 18,700 26,500 46,500

150X increase in die per wafer

ECE 410, Prof. A. Mason Lecture Notes Page i.15
 Semi-Conductor Scaling

Modern CMOS
10 um
Beginning of
Submicron CMOS
Deep UV Litho
1 um
90 nm in 2004
37 Years
of Scaling History 65 nm in 2006

100 nm Every generation

Feature size shrinks by 70% Presumed Limit
Transistor density doubles to Scaling
Wafer cost increases by 20%
Chip cost comes down by 40%
10 nm
Generations occur regularly
On average every 2.9 years
over the past 35 years
Recently every 2 years
1 nm
1970 1980 1990 2000 2010 2020

ECE 410, Prof. A. Mason Lecture Notes Page i.16

Example 65 nm Product: DSP chip

Features:
• Die Size: 13.3mm2
• 5.9M bits SRAM
• 1.9M gates of logic
¾ eFuse (dieID) and repair
¾ ARM7 uC
¾ LEAD3 DSP (250K gates)
¾ MegaCell (300K gates)
¾ ASIC gates (1.3M gates)
• In Volume Production

ECE 410, Prof. A. Mason Lecture Notes Page i.17

 The Impending Constraint: Power Consumption
Pwr_Active = Cap*Voltage2*Freq + Leakage
- Cap: Decrease with technology advance
- Voltage: Nearly constant, possibly at minimum now
- Freq: Increases with technology advance
- Leakage: Increases with technology advance & with temperature (caused
by higher power)

Pwr_Idle = Leakage
- Leakage: Increases with technology advance & with temperature
MHz Phone Performance Requirement Power vs. Technology
700 10000
MCU Without PM
600
With PM
1000

Leakage Power
500

400
100
300

200
10
100 Product
available
0 1
180nm 130nm 90nm 65nm 45nm
1993 1995 1997 1999 2001 2003 2005 2007

ECE 410, Prof. A. Mason Lecture Notes Page i.18

 Power Supply Trends
Digital Core Voltage Projections
1.8 V from the 2000 ITRS*
1.5 V

1.2 V

0.9 V

0.6 V 0.6 V

Year 1999 2001 2004 2008 2011 2014

Feature Size (nm) 180 130 90 60 40 30
* http://public.itrs.net/Files/2000UpdateFinal/ORTC2000final.pdf

• Data from projections in 2000

• Actually
– reached 65nm in 2006 and 45nm in 2008, way ahead of
projections

ECE 410, Prof. A. Mason Lecture Notes Page i.19