CSE 370 Spring 2006

Introduction to Digital Design

Lecture 21: Sequential Logic
Technologies
Last Lecture
Moore and Mealy Machines

Today
Sequential logic technologies

Vending machine: Moore to synch. Mealy

OPEN = Q1Q0 creates a combinational delay after Q1 and
Mealy and Moore examples
Q0 change in Moore implementation
This can be corrected by retiming, i.e., move flip-flops and
logic through each other to improve delay Recognize A,B = 0,1
OPEN.d = (Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D) Mealy or Moore? A
out

= Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D B

Implementation now looks like a synchronous Mealy machine

it is common for programmable devices to have FF at end
of logic A
D Q
out
B
clock
Q
A
D Q out

B
D Q
clock
Q
 Mealy and Moore examples
(cont’d) HDLs and Sequential Logic
Flip-flops
Recognize A,B = 1,0 then 0,1
representation of clocks - timing of state changes
Mealy or Moore? out
asynchronous vs. synchronous
A
D Q FSMs
Q
structural view (FFs separate from combinational logic)
B
D Q

Q
behavioral view (synthesis of sequencers – not in this
clock
course)
out
Data-paths = data computation (e.g., ALUs, comparators)
A
D Q D Q + registers
Q Q

B
use of arithmetic/logical operators
D Q D Q

Q Q control of storage elements

clock

Verilog FSM - Reduce 1s

Example: reduce-1-string-by-1
example
Remove one 1 from every string of 1s on the input Moore machine state assignment
(easy to change,
module reduce (clk, reset, in, out); if in one place)
input clk, reset, in;
Moore Mealy output out;

parameter zero = 2’b00;

parameter one1 = 2’b01;
zero parameter two1s = 2’b10; zero
[0] 0/0
zero [0]
reg out;
1 0 [0] reg [2:1] state; // state variables 1 0
reg [2:1] next_state;
0 one1 0/0 1/0 0 one1
[0] always @(posedge clk)
[0]
one1 if (reset) state = zero;
0 1 [0] 0
1/1
else state = next_state; 1
1 1
two1s two1s
[1] [1]
 Moore Verilog FSM (cont’d) Mealy Verilog FSM
module reduce (clk, reset, in, out);
input clk, reset, in;
always @(in or state) output out;
crucial to include reg out;
case (state) all signals that are reg state; // state variables
zero: reg next_state;
// last input was a zero input to state determination
begin always @(posedge clk)
if (in) next_state = one1; if (reset) state = zero;
else next_state = zero; else state = next_state;
end 0/0
one1: note that output always @(in or state) zero
case (state) [0]
// we've seen one 1 depends only on state zero: // last input was a zero
begin
begin 1/0
if (in) next_state = two1s; out = 0; 0/0
else next_state = zero; if (in) next_state = one;
end else next_state = zero; one1
two1s: always @(state) end [0]
// we've seen at least 2 ones one: // we've seen one 1 1/1
case (state)
begin zero: out = 0; if (in) begin
if (in) next_state = two1s; one1: out = 0; next_state = one; out = 1;
else next_state = zero; two1s: out = 1; end else begin
end next_state = zero; out = 0;
endcase
endcase end
endcase
endmodule endmodule

Finite state machines summary

Synchronous Mealy Machine
module reduce (clk, reset, in, out); Models for representing sequential circuits
input clk, reset, in;
output out; abstraction of sequential elements
reg out;
reg state; // state variables finite state machines and their state diagrams
always @(posedge clk)
if (reset) state = zero;
inputs/outputs
else
case (state) Mealy, Moore, and synchronous Mealy machines
zero: // last input was a zero
begin Finite state machine design procedure
out = 0;
if (in) state = one; deriving state diagram
else state = zero;
end
one: // we've seen one 1
deriving state transition table
if (in) begin
state = one; out = 1;
determining next state and output functions
end else begin
state = zero; out = 0; implementing combinational logic
end
endcase Hardware description languages
endmodule
Sequential logic implementation Median filter FSM
Implementation Remove single 0s between two 1s (output = NS3)
random logic gates and FFs 0 I PS1 PS2 PS3 NS1 NS2 NS3
0 0 0 0 0 0 0
programmable logic devices (PAL with FFs) Reset
0 0 0 1 0 0 0
000 0 0 1 0 0 0 1
Design procedure 0 0 1 1 0 0 1
0 1 0 1 0 0 0 1 0
state diagrams 0 1 0 1 X X X
100 0 1 1 0 0 1 1
state transition table 0 1 0 1 1 1 0 1 1
1 1 0 0 0 1 0 0
state assignment 1 0 0 1 1 0 0
010 110 1 0 1 0 1 1 1
next state functions 0 1 1 0 1 0 1 1 1 1 1
1 1 0 0 1 1 0
0 1 1 0 1 X X X
001 1 111 011 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1
0

Median filter FSM (cont’d) Median filter FSM (cont’d)

Realized using the standard procedure and individual But it looks like a shift register if you look at it right
FFs and gates
0 0
I PS1 PS2 PS3 NS1 NS2 NS3
0 0 0 0 0 0 0 Reset Reset
0 0 0 1 0 0 0 000 000
0 0 1 0 0 0 1 1 1
0 0 1 1 0 0 1 0 0
NS1 = Reset’ (I)
0 1 0 0 0 1 0 100 100 0
NS2 = Reset’ ( PS1 + PS2 I ) 101
0 1 0 1 X X X 0 1 0
0 1 1 0 0 1 1 NS3 = Reset’ PS2 1
0 1 1 1 0 1 1 1 1 1
O = PS3 1
1 0 0 0 1 0 0 010 110 010 110
1 0 0 1 1 0 0 0 1 1 0 0 1 0
1 0 1 0 1 1 1
1 0 1 1 1 1 1 0 0
1 1 0 0 1 1 0 001 1 111 011 001 1 111 011 1
1 1 0 1 X X X 1
1 1 1 0 1 1 1 0 0
1 1 1 1 1 1 1
 Median filter FSM (cont’d) Implementation using PALs
Programmable logic building block for sequential logic
An alternate implementation with S/R FFs
macro-cell: FF + logic
D-FF
Reset
R = Reset two-level logic capability like PAL (e.g., 8 product
S = PS2 In
NS1 = In
terms)
NS2 = PS1
R S R S R S NS3 = PS2
In D Q D Q D Q Out O = PS3
DQ
CLK Q

The set input (S) does the median filter function by

making the next state 111 whenever the input is 1 and
PS2 is 1 (1 input to state x1x)

Vending machine example Vending machine (synch. Mealy

(Moore PLD mapping) PLD mapping)
D0 = reset'(Q0'N + Q0N' + Q1N + Q1D)
OPEN = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
D1 = reset'(Q1 + D + Q0N) CLK CLK
OPEN = Q1Q0
Q0 Q0
DQ DQ

Seq Seq
N N

Q1 Q1
DQ DQ

Seq Seq
D D

Open OPEN Open

DQ DQ

Com Seq
Reset Reset
22V10 PAL 22V10 PAL Macro Cell
Combinational logic Sequential logic element + output/input selection
elements (SoP)
Sequential logic
elements (D-FFs)
Up to 10 outputs
Up to 10 FFs
Up to 22 inputs

Light Game FSM Verilog

Light Game FSM module Light_Game (LEDS, LPB, RPB, CLK, RESET);

input LPB ;
input RPB ;
Tug of War game combinational logic
input CLK ; wire L, R;
7 LEDs, 2 push buttons (L, R) input RESET; assign L = ~left && LPB;
output [6:0] LEDS ; assign R = ~right && RPB;
assign LEDS = position;

reg [6:0] position;

RESET reg left;
reg right; sequential logic
always @(posedge CLK)
R R R R R
begin
LED LED LED LED LED LED LED
left <= LPB;
(6) (5) (4) (3) (2) (1) (0)
L L L L L right <= RPB;
if (RESET) position <= 7'b0001000;
else if ((position == 7'b0000001) || (position == 7'b1000000)) ;
else if (L) position <= position << 1;
else if (R) position <= position >> 1;
end

endmodule
 Example: traffic light controller Example: traffic light
A busy highway is intersected by a little used farmroad
Detectors C sense the presence of cars waiting on the farmroad controller (cont’)
with no car on farmroad, light remain green in highway direction Highway/farm road intersection
if vehicle on farmroad, highway lights go from Green to Yellow
to Red, allowing the farmroad lights to become green farm road
these stay green only as long as a farmroad car is detected but
never longer than a set interval car sensors
when these are met, farm lights transition from Green to Yellow
to Red, allowing highway to return to green
even if farmroad vehicles are waiting, highway gets at least a highway
set interval as green
Assume you have an interval timer that generates:
a short time pulse (TS) and
a long time pulse (TL),
in response to a set (ST) signal.
TS is to be used for timing yellow lights and TL for green lights

Example: traffic light Example: traffic light

controller (cont’) controller (cont’)
Tabulation of inputs and outputs State diagram
(TL•C)' Reset
inputs description outputs description
reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights
C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights
TS short time interval expired ST start timing a short or long interval HG
TL long time interval expired
TL•C / ST TS / ST
Tabulation of unique states – some light configurations imply
others TS' HY FY TS'

state description
HG highway green (farm road red) TS / ST TL+C' / ST
HY highway yellow (farm road red) FG
FG farm road green (highway red)
FY farm road yellow (highway red)
(TL+C')'
 Example: traffic light Logic for different state
controller (cont’) assignments
Generate state table with symbolic states SA1
NS1 = C•TL'•PS1•PS0 + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0
output encoding – similar problem NS0 = C•TL•PS1'•PS0' + C•TL'•PS1•PS0 + PS1'•PS0
Consider state assignments to state assignment
(Green = 00, Yellow = 01, Red = 10) ST = C•TL•PS1'•PS0' + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0
Inputs Present State Next State Outputs H1 = PS1 H0 = PS1'•PS0
F1 = PS1' F0 = PS1•PS0‘
C TL TS ST H F
0 – – HG HG 0 Green Red
SA2
– 0 – HG HG 0 Green Red
NS1 = C•TL•PS1' + TS'•PS1 + C'•PS1'•PS0
1 1 – HG HY 1 Green Red NS0 = TS•PS1•PS0' + PS1'•PS0 + TS'•PS1•PS0
– – 0 HY HY 0 Yellow Red
– – 1 HY FG 1 Yellow Red ST = C•TL•PS1' + C'•PS1'•PS0 + TS•PS1
1 0 – FG FG 0 Red Green H1 = PS0 H0 = PS1•PS0'
0 – – FG FY 1 Red Green F1 = PS0' F0 = PS1•PS0
– 1 – FG FY 1 Red Green
– – 0 FY FY 0 Red Yellow SA3
– – 1 FY HG 1 Red Yellow NS3 = C'•PS2 + TL•PS2 + TS'•PS3 NS2 = TS•PS1 + C•TL'•PS2
NS1 = C•TL•PS0 + TS'•PS1 NS0 = C'•PS0 + TL'•PS0 + TS•PS3
SA1: HG = 00 HY = 01 FG = 11 FY = 10 ST = C•TL•PS0 + TS•PS1 + C'•PS2 + TL•PS2 + TS•PS3
SA2: HG = 00 HY = 10 FG = 01 FY = 11 H1 = PS3 + PS2 H0 = PS1
SA3: HG = 0001 HY = 0010 FG = 0100 FY = 1000 (one-hot) F1 = PS1 + PS0 F0 = PS3