EE2000 Logic Circuit Design

Lecture 9 – Sequential Logic Circuit

Design

1
State Transition Tables
𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State 𝐽𝐽 𝐾𝐾 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold 0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
0 1 0 1 Reset 0 1 0 1 Reset
1 0 1 0 Set 1 0 1 0 Set
1 1 1 1 Undefined 1 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle

𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State 𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State

1 1 0 Set 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
0 0 1 Reset 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle

2
Outline
9.1 Finite State Machines
- Concept of States
- Mealy vs Moore machines
- State table and diagram
9.2 Sequential Circuit Analyzer
9.3 Sequential Circuit Design
- Design example
- State minimization

3
Sequential and Combinational Circuits
Combinational logic circuit
Output depends only on the inputs (As discussed in
previous lectures)
Sequential logic circuit
Output depends on present input + past history
Memory circuit (to store previous STATE information)
is required

4
9.1 Finite State Machines - Concept
Current
state State
Next state memory Output Outputs
Logic Logic
Inputs

Clk

• A generic model/tool used in sequential circuit design

• State: Status of all memory units in the circuit. (n flip-
flops → 2n states)
– 1 Flip-Flop: 0 or 1 (Two states)
– 2 Flip-Flops: 0 & 0, 0 & 1, 1 & 0 or 1 & 1 (Four
states) 5
9.1 Finite State Machines - Concept

Current
state State
Next state memory Output Outputs
Logic Logic
Inputs

Clk

• Next State Logic: A combinational logic function to

determine the next state of the system
• Output Logic: A combinational logic function to
produce the outputs

6
Example
Next State Combinational Circuit

Inputs

Outputs

Output
Combinational
Circuit

7
Mealy and Moore Machines
Mealy machine Output depends on the current state
and input
Next Outputs
State Output
Inputs state memory Logic
Logic

Clk

Moore machine Output depends only on the current

state
Next Outputs
State Output
Inputs state memory Logic
Logic

Clk 8
Examples (Mealy or Moore?)
(a)

(b) out
A DQ DQ
Q Q
B DQ DQ (c)
Q Q
clock

9
State Diagram

𝑆𝑆𝑖𝑖 represents a state

represents a transition from

𝑆𝑆𝑖𝑖 𝑆𝑆𝑗𝑗
state 𝑆𝑆𝑖𝑖 to 𝑆𝑆𝑗𝑗

Mealy machine Moore machine

𝑥𝑥/𝑧𝑧 𝑥𝑥
𝑆𝑆𝑖𝑖 𝑆𝑆𝑗𝑗 𝑆𝑆𝑖𝑖 /𝑧𝑧𝑖𝑖 𝑆𝑆𝑗𝑗 /𝑧𝑧𝑗𝑗

𝑥𝑥 is input 𝑥𝑥 is input
𝑧𝑧 is output 𝑧𝑧𝑖𝑖 is output
(output depends on input) Output is independent on input
10
Example (Mealy Machine)
State diagram

State table
Present Next State Output Z Present Input X
State Input Input Input Input State 0 1
X=0 X=1 X=0 X=1
SA SB/1 SC/0
SA SB SC 1 0
SB SB/0 SA/1
SB SB SA 0 1
SC SA/0 SC/0
SC SA SC 0 0
11
Example (Mealy Machine)
Given the initial state is 𝑆𝑆𝐴𝐴 , work out how
will the circuit behave with an input
sequence of 011010.

12
Example (Mealy Machine)
Given the initial state is 𝑆𝑆𝐴𝐴 , work out how
will the circuit behave with an input
sequence of 011010.

𝑆𝑆𝐵𝐵 𝑆𝑆𝐴𝐴 𝑆𝑆𝐶𝐶 𝑆𝑆𝐴𝐴 𝑆𝑆𝐶𝐶

1 1 0 0 0 0
𝑆𝑆𝐵𝐵 𝑆𝑆𝐴𝐴 𝑆𝑆𝐶𝐶 𝑆𝑆𝐴𝐴 𝑆𝑆𝑐𝑐 𝑆𝑆𝐴𝐴

13
Example (Moore Machine)

Present State Input X Present

0 1 Output Z

SW SY SX 0
SX SX SY 1
SY SX SW 0

14
Example (Moore Machine)
Given the initial state is 𝑆𝑆𝑊𝑊 , work out how
will the circuit behave with an input
sequence of 011010.

15
Example (Moore Machine)
Given the initial state is 𝑆𝑆𝑊𝑊 , work out how
will the circuit behave with an input
sequence of 011010.

𝑆𝑆𝑌𝑌 𝑆𝑆𝑊𝑊 𝑆𝑆𝑋𝑋 𝑆𝑆𝑋𝑋 𝑆𝑆𝑌𝑌

0 0 0 1 1 0
𝑆𝑆𝑌𝑌 𝑆𝑆𝑊𝑊 𝑆𝑆𝑋𝑋 𝑆𝑆𝑋𝑋 𝑆𝑆𝑌𝑌 𝑆𝑆𝑋𝑋

16
Tables (Example of SR FF)
Truth table Excitation table
𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡+1 𝑆𝑆𝑡𝑡 𝑆𝑆𝑡𝑡+1 𝑆𝑆 𝑅𝑅
0 0 0 0 𝑆𝑆0 𝑆𝑆0 0 X State transition
0 0 1 1 𝑆𝑆0 𝑆𝑆1 1 0 based on inputs
0 1 0 0 𝑆𝑆1 𝑆𝑆0 0 1 S0: Q = 0
0 1 1 0 𝑆𝑆1 𝑆𝑆1 X 0 S1: Q = 1
1 0 0 1
1 0 1 1 State table
1 1 0 x Present Input S R Present
State 00 01 10 1 1 Output 𝑸𝑸𝒕𝒕
1 1 1 x
𝑆𝑆0 𝑆𝑆0 𝑆𝑆0 𝑆𝑆1 x 0
Outputs based
𝑆𝑆1 𝑆𝑆1 𝑆𝑆0 𝑆𝑆1 x 1
on inputs
States, Input/Transition, Outputs
17
Example (SR-FF)
State table
𝑺𝑺 𝑹𝑹 𝑸𝑸𝒕𝒕+𝟏𝟏 𝑸𝑸𝒕𝒕+𝟏𝟏 State
Present Input S R Present
0 0 𝑸𝑸𝒕𝒕 𝑸𝑸𝒕𝒕 Hold
State 00 01 10 1 1 Output 𝑸𝑸𝒕𝒕
0 1 0 1 Reset
0 0 0 1 x 0
1 0 1 0 Set
1 1 0 1 x 1
1 1 0 0 Undefined

State diagram Characteristic equation

𝑄𝑄𝑡𝑡∗
𝑆𝑆 𝑅𝑅
𝑄𝑄𝑡𝑡∗ = 𝑆𝑆 + 𝑅𝑅𝑅𝑄𝑄𝑡𝑡
0x x0 𝑄𝑄𝑡𝑡
0 0 x 1

1 0 x 1
18
Other FFs
State diagram
1
𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
0 1
1 1 0 Set
0 0 1 Reset 0
D-FF
𝐽𝐽 𝐾𝐾 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State 11
1X
0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
0X X0
0 1 0 1 Reset
1 0 1 0 Set X1
11
1 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle JK-FF
1
𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
0 0
0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle 1
T-FF 19
Exercise (Other FFs)
State diagram Characteristic equation
1
0 1
0
D-FF
11

11
JK-FF
1
0 0
1
T-FF 20
9.2 Sequential Circuit Analyzer

Given a sequential circuit, analyze its behavior by producing

the state diagram and state table.

21
Example

STEP 1: Which state machine? Mealy or Moore?

STEP 2: Input(s)? Output(s)? No of FF(s)? How many
states?
22
Example

STEP 3: Determine the flip-flop input function

STEP 4: Determine the output function

23
Example
STEP 5: Fill in the Analysis Table
Present State (PS) Input Flip-Flops’ Excitations Next State (NS) Present
Output
State (𝑸𝑸𝑨𝑨 𝑸𝑸𝑩𝑩 ) 𝑿𝑿 𝑱𝑱𝑨𝑨 𝑲𝑲𝑨𝑨 𝑱𝑱𝑩𝑩 𝑲𝑲𝑩𝑩 𝑄𝑄𝐴𝐴∗ 𝑄𝑄𝐵𝐵∗ 𝒁𝒁
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1

24
Example
STEP 5: Fill in the Analysis Table
Present State (PS) Input Flip-Flops’ Excitations Next State (NS) Present
Output
State (𝑸𝑸𝑨𝑨 𝑸𝑸𝑩𝑩 ) 𝑿𝑿 𝑱𝑱𝑨𝑨 𝑲𝑲𝑨𝑨 𝑱𝑱𝑩𝑩 𝑲𝑲𝑩𝑩 𝑄𝑄𝐴𝐴∗ 𝑄𝑄𝐵𝐵∗ 𝒁𝒁
0 0 0 1 0
0 0
1 0 0 0 1
0 1 1 1 0
0 1
1 1 0 0 1
0 0 0 1 1
1 0
1 0 0 0 0
0 1 1 1 1
1 1
1 1 0 0 0

25
Example
STEP 5: Fill in the Analysis Table
Present State (PS) Input Flip-Flops’ Excitations Next State (NS) Present
Output
State (𝑸𝑸𝑨𝑨 𝑸𝑸𝑩𝑩 ) 𝑿𝑿 𝑱𝑱𝑨𝑨 𝑲𝑲𝑨𝑨 𝑱𝑱𝑩𝑩 𝑲𝑲𝑩𝑩 𝑄𝑄𝐴𝐴∗ 𝑄𝑄𝐵𝐵∗ 𝒁𝒁
0 0 0 1 0 (0 1)
0 0
1 0 0 0 1 (0 0)
0 1 1 1 0 (1 1)
0 1
1 1 0 0 1 (1 0)
0 0 0 1 1 (1 1)
1 0
1 0 0 0 0 (1 0)
0 1 1 1 1 (0 0)
1 1
1 1 0 0 0 (1 1)

26
Example
STEP 5: Fill in the Analysis Table
Present State (PS) Input Flip-Flops’ Excitations Next State (NS) Present
Output
State (𝑸𝑸𝑨𝑨 𝑸𝑸𝑩𝑩 ) 𝑿𝑿 𝑱𝑱𝑨𝑨 𝑲𝑲𝑨𝑨 𝑱𝑱𝑩𝑩 𝑲𝑲𝑩𝑩 𝑄𝑄𝐴𝐴∗ 𝑄𝑄𝐵𝐵∗ 𝒁𝒁
0 0 0 1 0 (0 1) 0
0 0
1 0 0 0 1 (0 0) 0
0 1 1 1 0 (1 1) 1
0 1
1 1 0 0 1 (1 0) 1
0 0 0 1 1 (1 1) 1
1 0
1 0 0 0 0 (1 0) 1
0 1 1 1 1 (0 0) 0
1 1
1 1 0 0 0 (1 1) 0

27
Example
STEP 6: Work out the State Table
Present State (PS) Input Next State (NS) Present
Output
State (𝑸𝑸𝑨𝑨 𝑸𝑸𝑩𝑩 ) 𝑿𝑿 𝑄𝑄𝐴𝐴∗ 𝑄𝑄𝐵𝐵∗ 𝒁𝒁
0 0 1 0 Present State Input X Present
0 0
1 0 0 0 0 1 Output Z
0 1 1 1 0 0 (0 1) (0 0) 0
0 1
1 1 0 1 0 1 (1 1) (1 0) 1
0 1 1 1 1 0 (1 1) (1 0) 1
1 0
1 1 0 1 1 1 (0 0) (1 1) 0
0 0 0 0
1 1
1 1 1 0

28
Example
STEP 7: Work out the State Diagram

Present State Input X Present

0 1 Output Z

0 0 (0 1) (0 0) 0
0 1 (1 1) (1 0) 1
1 0 (1 1) (1 0) 1
1 1 (0 0) (1 1) 0

29
Exercise
Work out the State Table and State Diagram of the
following circuit Present State Input X
𝑄𝑄1 𝑄𝑄2 0 1
0 0
0 1
1 0
1 1

30
9.3 Sequential Circuit Design

(a) How many outputs?

(b) How many states?
(c) Mealy or Moore machine?

31
Traffic Light Circuit

32
Example (Sequence Detector)
Design a Moore machine to detect the sequence “111”
(Overlapping)
In other words,
Design a system with one input 𝑥𝑥 and one output 𝑧𝑧 such
that 𝑧𝑧 = 1 if 𝑥𝑥 has been 1 for at least three consecutive
clock times.
𝑥𝑥 0 1 1 0 1 1 1 0 1 1 1 1 1 0
𝑧𝑧 0 0 0 0 0 0 0 1 0 0 0 1 1 1

33
Example (Sequence Detector)
𝑥𝑥 0 1 1 0 1 1 1 0 1 1 1 1 1 0
𝑧𝑧 0 0 0 0 0 0 0 1 0 0 0 1 1 1

STEP 1: Determine what needs to be stored in memory

and how to store them.
A: Input is ‘0’
B: one ‘1’ is detected
C: two ‘1’s are detected
D: three ‘1’s are detected and output 1

34
Example (Sequence Detector)
STEP 2: Work out the State Diagram
A: Input is ‘0’
B: one ‘1’ is detected
C: two ‘1’s are detected
D: three ‘1’s are detected and output 1
1

0 D/1 1

0
A/0 C/0
0
1
1
0 B/0 35
Example (Sequence Detector)
STEP 3: Work out analysis table with assigned FFs
4 states → 2 FFs (We use D-FFs in this example)
Present Next stage
Input Present
State
X 𝑸𝑸∗𝟏𝟏 𝑸𝑸∗𝟐𝟐 Output Z
(𝑸𝑸𝟏𝟏 𝑸𝑸𝟐𝟐 )
A (0 0) 0 0 0 0
A (0 0) 1 0 1 0
B (0 1) 0 0 0 0
B (0 1) 1 1 0 0
C (1 0) 0 0 0 0
C (1 0) 1 1 1 0
Assign State A: D (1 1) 0 0 0 1

𝑄𝑄1 → 0 and 𝑄𝑄2 → 0 etc D (1 1) 1 1 1 1

36
Example (Sequence Detector)
𝑄𝑄1∗
STEP 4: Work out 𝐷𝐷1 and 𝐷𝐷2 𝑄𝑄1 𝑄𝑄2
𝑥𝑥
Present Next stage 0 0 0 0
Input Present
State
X 𝑸𝑸∗𝟏𝟏 𝑸𝑸∗𝟐𝟐 Output Z
(𝑸𝑸𝟏𝟏 𝑸𝑸𝟐𝟐 ) 0 1 1 1
A (0 0) 0 0 0 0
A (0 0) 1 0 1 0
𝐷𝐷1 = 𝑄𝑄1∗ = 𝑥𝑥(𝑄𝑄1 +𝑄𝑄2 )
B (0 1) 0 0 0 0 𝑄𝑄2∗
𝑄𝑄1 𝑄𝑄2
B (0 1) 1 1 0 0
𝑥𝑥
C (1 0) 0 0 0 0
0 0 0 0
C (1 0) 1 1 1 0
D (1 1) 0 0 0 1 1 0 1 1
D (1 1) 1 1 1 1
𝐷𝐷2 = 𝑄𝑄2∗ = 𝑥𝑥(𝑄𝑄1 +𝑄𝑄2′ )
37
Example (Sequence Detector)
𝑧𝑧
STEP 5: Work out 𝑧𝑧 𝑄𝑄1 𝑄𝑄2
𝑥𝑥
Present Next stage 0 0 1 0
Input Present
State
X 𝑸𝑸∗𝟏𝟏 𝑸𝑸∗𝟐𝟐 Output Z
(𝑸𝑸𝟏𝟏 𝑸𝑸𝟐𝟐 ) 0 0 1 0
A (0 0) 0 0 0 0
A (0 0) 1 0 1 0 𝑧𝑧 = 𝑄𝑄1 𝑄𝑄2
B (0 1) 0 0 0 0
B (0 1) 1 1 0 0
C (1 0) 0 0 0 0
C (1 0) 1 1 1 0
D (1 1) 0 0 0 1
D (1 1) 1 1 1 1

38
Example (Sequence Detector)
STEP 6: Draw the sequential logic circuits
𝐷𝐷1 = 𝑥𝑥(𝑄𝑄1 +𝑄𝑄2 ) 𝐷𝐷2 = 𝑥𝑥(𝑄𝑄1 +𝑄𝑄2′ ) 𝑧𝑧 = 𝑄𝑄1 𝑄𝑄2

𝑥𝑥 𝑧𝑧
𝑄𝑄1

𝑄𝑄2

clk

39
Exercise (Sequence Detector)
Design a Mealy machine to detect the sequence “111”
(Overlapping)
In other words,
Design a system with one input 𝑥𝑥 and one output 𝑧𝑧 such
that 𝑧𝑧 = 1 if 𝑥𝑥 has been 1 for at least three consecutive
clock times.
𝑥𝑥 0 1 1 0 1 1 1 0 1 1 1 1 1 0
𝑧𝑧 0 0 0 0 0 0 1 0 0 0 1 1 1 0

40
Exercise (Sequence Detector)
𝑥𝑥 0 1 1 0 1 1 1 0 1 1 1 1 1 0
𝑧𝑧 0 0 0 0 0 0 1 0 0 0 1 1 1 0

STEP 1: Determine what needs to be stored in memory

and how to store them.

41
Exercise (Sequence Detector)
STEP 2: Work out the State Diagram

42
Exercise (Sequence Detector)
STEP 3: Work out the analysis table with assigned FFs
3 states → 2 FFs (We use D-FFs in this example)
Present Next stage
Input Present
State
X 𝑸𝑸∗𝟏𝟏 𝑸𝑸∗𝟐𝟐 Output Z
(𝑸𝑸𝟏𝟏 𝑸𝑸𝟐𝟐 )

Assign State A:
𝑄𝑄1 → 0 and 𝑄𝑄2 → 0 etc
43
Exercise (Sequence Detector)
STEP 4: Work out 𝐷𝐷1 and 𝐷𝐷2
𝑄𝑄1∗ 𝑄𝑄2∗
𝑄𝑄1 𝑄𝑄2 𝑄𝑄1 𝑄𝑄2
𝑥𝑥 𝑥𝑥

𝐷𝐷1 = 𝑄𝑄1∗ 𝐷𝐷2 = 𝑄𝑄2∗

𝑧𝑧
𝑄𝑄1 𝑄𝑄2
STEP 5: Work out 𝑧𝑧
𝑥𝑥

𝑧𝑧 =
44
Exercise (Sequence Detector)
STEP 6: Draw the sequential logic circuits

45
Exercise (Sequence Detector)
Use T FFs to design a Mealy machine to detect the
sequence “111” (Overlapping)
Present State Next stage Flip-Flops
Input X Present Output Z
(𝑸𝑸𝟏𝟏 𝑸𝑸𝟐𝟐 ) 𝑸𝑸∗𝟏𝟏 𝑸𝑸∗𝟐𝟐 𝑻𝑻𝟏𝟏 𝑻𝑻𝟐𝟐
A (0 0) 0 0 0 0
A (0 0) 1 0 1 0
B (0 1) 0 0 0 0
B (0 1) 1 1 1 0
(1 0) x x x x
C (1 1) 0 0 0 0
C (1 1) 1 1 1 1

46
Exercise (Sequence Detector)
𝑇𝑇1
𝑄𝑄1 𝑄𝑄2
𝑥𝑥

𝑇𝑇1 =
𝑇𝑇2
𝑄𝑄1 𝑄𝑄2
𝑥𝑥

𝑇𝑇2 =
47
Exercise (Sequence Detector)
Use JK FFs to design a Mealy machine to detect the
sequence “111” (Overlapping)
Present Next
Input Flip-Flops Present
State stage
X Output Z
(𝑸𝑸𝟏𝟏 𝑸𝑸𝟐𝟐 ) 𝑸𝑸∗𝟏𝟏 𝑸𝑸∗𝟐𝟐 𝑱𝑱𝟏𝟏 𝑲𝑲𝟏𝟏 𝑱𝑱𝟐𝟐 𝑲𝑲𝟐𝟐
A (0 0) 0 0 0 0
A (0 0) 1 0 1 0
B (0 1) 0 0 0 0
B (0 1) 1 1 1 0
(1 0) x x x x
C (1 1) 0 0 0 0
C (1 1) 1 1 1 1

48
𝐽𝐽1 𝐽𝐽2
𝑄𝑄1 𝑄𝑄2 𝑄𝑄1 𝑄𝑄2
𝑥𝑥 𝑥𝑥

𝐽𝐽1 = 𝐽𝐽1 =
𝐾𝐾1 𝐾𝐾2
𝑄𝑄1 𝑄𝑄2 𝑄𝑄1 𝑄𝑄2
𝑥𝑥 𝑥𝑥

𝐾𝐾1 = 𝐾𝐾2 =
49
Mealy vs Moore Machines
Mealy machine Moore machine
Present Input X Present State Input X Present
State 0 1 0 1 Output Z
A A/0 B/0 A A B 0
B A/0 C/0 B A C 0
C A/0 C/1 C A D 0
D A D 1
Moore machine
- Typically more states, more complex logic circuits

Mealy machine
+ Typically fewer states, simpler logic circuits
50
Example (Timing Diagram) 𝑧𝑧 = 𝑄𝑄1 𝑄𝑄2

Clk
Present
A
state
Input 𝑥𝑥
Next
state
Output 𝑧𝑧 1

51
Example (Timing Diagram) 𝑧𝑧 = 𝑄𝑄1 𝑄𝑄2

Clk
Present
A B C D D D D D A B C A B C
state
Input 𝑥𝑥 1 1 1 1 1 1 1 0 1 1 0 1 1 1
Next
B C D D D D D A B C A B C D
state
Output 𝑧𝑧 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1

52
Exercise (Timing Diagram) 𝑧𝑧 = 𝑥𝑥𝑄𝑄1

Clk
Present
A
state
Input 𝑥𝑥
Next
state
𝑄𝑄1

Output 𝑧𝑧
53
Mealy vs Moore Machines
Clk

Input 𝑥𝑥 1 1 1 1 1 1 1 0 1 1 0 1 1 1

Moore
Output 𝑧𝑧 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1

Mealy
Output 𝑧𝑧 0 0 1 1 1 1 1 0 0 0 0 0 0 1

Observation
- Moore: Output changes occur only after clk edge
- Mealy: Output changes occur whenever input changes
- Mealy: Faster response but glitch might occurs
54
Mealy vs Moore Machines
Mealy machine Moore machine
Output depends on inputs and Output depends only on
present state present state
Typically fewer states, simpler Typically more states, more
logic circuits complex logic circuits
React faster to inputs React one clock cycle later
Asynchronous Synchronous
Glitches might present No glitch

Better solution?
Synchronous Mealy machine
55
Exercise (Sequence Detector)
Design a Moore machine to detect the sequence “11” or
“000” (Overlapping)
In other words,
Design a system with one input 𝑥𝑥 and one output 𝑧𝑧 such
that 𝑧𝑧 = 1 if 𝑥𝑥 has been 1 for at least two consecutive
clock times or 0 for at least three consecutive clock times.
𝑥𝑥 0 0 0 0 1 0 1 1 0 0 1 1 1 0
𝑧𝑧 ? ? ? 1 1 0 0 0 1 0 0 0 1 1

56
Exercise (Sequence Detector)
𝑥𝑥 0 0 0 0 1 0 1 1 0 0 1 1 1 0
𝑧𝑧 ? ? ? 1 1 0 0 0 1 0 0 0 1 1

(Hint: 5 states)

57
Exercise (Sequence Detector)
Design a Mealy machine to detect the sequence “00110”
(No overlapping)
In other words,
Design a system with one input 𝑥𝑥 and one output 𝑧𝑧 such
that 𝑧𝑧 = 1 if 𝑥𝑥 has been 0 for two consecutive clock times,
follows by two 1’s and then a 0.
𝑥𝑥 0 0 1 1 0 0 1 1 0 0 1 1 0 1
𝑧𝑧 0 0 0 0 1 0 0 0 0 0 0 0 1 0

58
Exercise (Sequence Detector)
𝑥𝑥 0 0 1 1 0 0 1 1 0 0 1 1 0 1
𝑧𝑧 0 0 0 0 1 0 0 0 0 0 0 0 1 0

(Hint: 5 states)

59
State Minimization
• No of FFs ∝ No of states
• Combinational logic complexity ∝ No of states
• More FFs, more complex logic circuits → higher COST!
• Solution: Aims to remove redundant states

60
State Minimization A
0
A/0
1
E/1
B E/1 C/0
• Direct observation C A/1 D/1
D F/0 G/1
Identify same output combinations and
E B/1 C/0
same state F F/0 E/1
G A/1 D/1
0 1 0 1 0 1
A A/0 E/1 A A/0 E/1 A A/0 E/1
B E/1 C/0 B E/1 C/0 B E/1 C/0
0 1
C A/1 D/1 C A/1 D/1 C A/1 D/1
A=F A/0 B/1
D F/0 G/1 D F/0 G/1 D F/0 G/1
B=E B/1 C/0
E B/1 C/0 E B/1 C/0 E B/1 C/0
C=G A/1 D/1
F F/0 E/1 F F/0 E/1 F F/0 E/1
D A/0 C/1
G A/1 D/1 G A/1 D/1 G A/1 D/1
61
Partitioning Method
0 1
A A/0 E/1
• Separate states with different outputs
B E/1 C/0 to different partitions
C A/1 D/1 𝑃𝑃0 = A B C D E F G
D F/0 G/1
E B/1 C/0 • A, D and F have outputs (0 1); B and E
F F/0 E/1 have outputs (1 0); C and G have
G A/1 D/1
outputs (1 1)
𝑃𝑃1 = A D F (B E)(C G)

62
Partitioning Method
P 0 1
𝑃𝑃1 = A D F (B E)(C G)
A A/0 E/1
1 D F/0 G/1 • Next check the next state of each state
F F/0 E/1
in each partition
B E/1 C/0
2 – A(0) → A (P1) A(1) → E (P2)
E B/1 C/0
C A/1 D/1 – D(0) → F (P1) D(1) → G (P3)
3
G A/1 D/1 – F(0) → F (P1) F(1) → E (P2)
∴ A and F same partitions; D is different

𝑃𝑃2 = A F (D)(B E)(C G)

63
Partitioning Method
P 0 1 𝑃𝑃2 = A F (D)(B E)(C G)
A A/0 E/1
1 This is the final with no more changes!
F F/0 E/1
B E/1 C/0
2
E B/1 C/0
I J
C A/1 D/1
3 A=F A/0 E/1
G A/1 D/1
B=E B/1 C/0
4 D F/0 G/1
C=G A/1 D/1
D F/0 G/1

64
Exercise
Present State Input X Present Reduce the state table using
0 1 Output Z
partitioning method
A I C 0
B B I 0 𝑃𝑃0 = A B C D E F G H I
C C G 0
D I C 1
Group states based on same
E D E 1
F I C 1
output
G E F 1
H H A 0
I A C 0

65
Exercise
Present State Input X Present Reduce the state table using
0 1 Output Z
partitioning method
𝑃𝑃1 =

66
Exercise
Present State Input X Present Reduce the state table using
0 1 Output Z
partitioning method
𝑃𝑃2 =

67
Exercise
Present State Input X Present Reduce the state table using
0 1 Output Z
partitioning method
𝑃𝑃3 =

68
Exercise
Present State Input X Present Reduce the state table using
Output Z
0 1 partitioning method

69
Implication Table
Present
State
Input X Present
Output Z
• Use a graphical grid to find equivalent
0 1
states
A D C 0
B F H 0 B
C E D 1
C
D A E 0
E C A 1 D
F F B 1
G B H 0 E
H C G 1
F
STEP 1: Construct an
G
implication table, label 𝑄𝑄2
to 𝑄𝑄𝑛𝑛 for each row and 𝑄𝑄1 H
to 𝑄𝑄𝑛𝑛−1 for each column
A B C D E F G 70
Implication Table e.g., Output of A is 0; Output
of C, E, F and H is 1. Put ‘X’ on
Present Input X Present B AC, AE, AF, and AH squares
State 0 1 Output Z

A D C 0 C X

B F H 0
D
C E D 1
D A E 0 E X
E C A 1
F X
F F B 1
G B H 0 G
H C G 1
H X
STEP 2: Compare each square.
A B C D E F G
If output is different for the
pair, put an ‘X’ to indicate
non-equivalence.
71
Implication Table
Present Input X Present B
State 0 1 Output Z

A D C 0 C X X

B F H 0 X
D
C E D 1
D A E 0 E X X X
E C A 1
F X X X
F F B 1
G B H 0 G X X X
H C G 1
H X X X X
STEP 2: Compare each square.
A B C D E F G
If output is different for the
pair, put an ‘X’ to indicate
non-equivalence.
72
Implication Table e.g., For square AB, when D =
F and C= H, they are
D-F
Present Input X Present B
C-H
equivalent.
State 0 1 Output Z

A D C 0 C X X

B F H 0 X
D
C E D 1
D A E 0 E X X X
E C A 1
F X X X
F F B 1
G B H 0 G X X X
H C G 1
H X X X X
STEP 3: Put implied pairs in
A B C D E F G
the remaining squares, such
that they must be equivalent
in order for the pair to be
73
equivalent.
Implication Table e.g., For square AB, when D =
F and C= H, they are
D-F
Present Input X Present B
C-H
equivalent.
State 0 1 Output Z

A D C 0 C X X

B F H 0 A-D A-F
D X
C-E E-H
C E D 1
C-E
D A E 0 E X X X
A-D
E C A 1 E-F C-F
F X X X
F F B 1 B-D A-B
G B H 0 B-D B-F A-B
G X X X
C-H H-H E-H
H C G 1
C-E C-C C-F
H X X X X
D-G A-G B-G
STEP 3: Put implied pairs in
A B C D E F G
the remaining squares, such
that they must be equivalent
in order for the pair to be
74
equivalent.
Implication Table
Present Input X Present D-F
B
State Output Z C-H
0 1
A D C 0 C X X

B F H 0 A-D A-F
D X
C-E E-H
C E D 1
C-E
D A E 0 E X X X
A-D
E C A 1 E-F C-F
F X X X
F F B 1 B-D A-B
G B H 0 B-D B-F A-B
G X X X
C-H H-H E-H
H C G 1
C-E C-C C-F
H X X X X
D-G A-G B-G
STEP 4: Remove self implied
A B C D E F G
pairs (A-D) in square AD and
same state pairs (H-H).
75
Implication Table
Present Input X Present D-F
B
State Output Z C-H
0 1
A D C 0 C X X

B F H 0 A-F
D C-E X
E-H
C E D 1
D A E 0 E X X A-D X
E C A 1 E-F C-F
F X X X
F F B 1 B-D A-B
G B H 0 B-D A-B
G B-F X X X
C-H E-H
H C G 1
C-E C-F
H X X X A-G X
D-G B-G
STEP 4: Remove self implied
A B C D E F G
pairs (A-D) in square AD and
same state pairs (H-H).
76
Implication Table e.g., For square AB, implied
pairs are D-F and C-H.
Present Input X Present D-F
B
C-H - Check squares D-F and C-H
State 0 1 Output Z
C X X - D-F is crossed
A D C 0
B F H 0 A-F → Cannot be implied
D C-E X
C E D 1
E-H - ‘X’ in square AB
D A E 0 E X X A-D X
E C A 1 E-F C-F
F X X X
F F B 1 B-D A-B
G B H 0 B-D A-B
G B-F X X X
C-H E-H
H C G 1
C-E C-F
H X X X A-G X
D-G B-G
STEP 5: Investigate each
A B C D E F G
square, put an ‘X’ if the
implied pairs that cannot be
implied.
77
Implication Table
Present Input X Present B X
State 0 1 Output Z

A D C 0 C X X

B F H 0 C-E X X
D
C E D 1
D A E 0 E X X A-D X
E C A 1 E-F C-F
F X X X
F F B 1 B-D A-B
G B H 0 B-D A-B
G X X X X
C-H E-H
H C G 1
C-E C-F
H X X X A-G X
D-G B-G
STEP 6: Repeat STEP 5…
A B C D E F G

78
Implication Table
Present Input X Present B X
State 0 1 Output Z

A D C 0 C X X

B F H 0 C-E X X
D
C E D 1
D A E 0 E X X A-D X
E C A 1
F X X X X X
F F B 1
G B H 0 G X X X X X X
H C G 1
C-E
H X X X A-G X X
D-G
STEP 6: Repeat STEP 5…
A B C D E F G

79
Implication Table
Present Input X Present B X
State 0 1 Output Z

A D C 0 C X X

B F H 0 C-E X X
D
C E D 1
D A E 0 E X X A-D X
E C A 1
F X X X X X
F F B 1
G B H 0 G X X X X X X
H C G 1
H X X X X X X X
STEP 6: Repeat STEP 5…
A B C D E F G

80
Implication Table Present
State
Input X
0 1
Present
Output Z

A A C 0
Present Input X Present
State Output Z B F H 0
0 1
C C D 1
A D C 0
B X F F B 1
B F H 0
G B H 0
C E D 1
C X X H C G 1
D A E 0
E C A 1 D C-E X X
F F B 1
G B H 0 E X X A-D X

H C G 1
F X X X X X
STEP 7: Combine equivalent X X X X X X
G
states
Square AD: A = D H X X X X X X X

Square CE: C = E A B C D E F G 81
Exercise
0 1 Reduce the state table using
A A/0 E/1 implication table method
B E/1 C/0
STEP 2: Compare each square.
C A/1 D/1
If output is different for the
D F/0 G/1 B pair, put an ‘X’ to indicate
E B/1 C/0
non-equivalence.
F F/0 E/1 C
G A/1 D/1
D

G
A B C D E F
82
VHDL for Finite State Machine

83
Example

entity seqckt is
port ( x: in std_logic; -- FSM input
z: out std_logic; -- FSM output
clk: in std_logic ); -- clock
end seqckt;

84
Output Logic

architecture behave of seqckt is

type states is (A,B,C); -- symbolic state names (enumerate)

signal state: states; --state variable

Begin

-- Output Logic

z <= ‘1’ when ((state = B) and (x = ‘1’)) --all conditions

or ((state = C) and (x = ‘1’)) --for which z = 1
else ‘0’; --otherwise z = 0

85
Next State Logic

86
Lab Session 4 (Week 12 or 13)
• Implement a simple finite-state machine with a good
coding style
• Implement two buttons to control the state change of
the FSM
• Display the state transition with the LEDs on the
Zedboard

87
VHDL Codes
Inputs
• clock signal (clk)
• Master reset button (rst)
• Control button (ctrlButton)

Output
• 8 LEDS for 8 states

88
VHDL Codes

89
VHDL Codes

90
Results

91
Test 2
• Cover Lecture 4 to 7
• 4 Questions 90 min
• Closed-book
• Two Venues (LT16 and LT3) – I will upload the seating list
on CANVAS later
• Place only stationery and your student ID card on the
table

92
PLD Diagram (Given in Test)

93
State Transition Table (Given in Test)

𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State 𝐽𝐽 𝐾𝐾 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State

0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold 0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
0 1 0 1 Reset 0 1 0 1 Reset
1 0 1 0 Set 1 0 1 0 Set
1 1 1 1 Undefined 1 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle

𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State 𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State

1 1 0 Set 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
0 0 1 Reset 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle

94
Assignment 3
• Submission deadline will change to Week 11 Sunday (2
Apr 2023) by 23:59
• More time to work on the assignment after TEST 2

95