Department of Electrical Engineering

Tutorial for Lab 2

EE-221: Digital Logic Design
Part (a): Getting Started with Verilog ModelSim

Part (b): Getting Started with Verilog HDL

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Part (a): Getting Started with Verilog ModelSim

1. Start the ModelSim

The startup screen looks like this:

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 2. Create a new project by File>New>Project

The Create Project window looks like this:

Edit project name, lab01 for example in this case.

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 Click OK
A new window Add items to Project appears. Select Create New File

Create Project File window appears

Type in a file name lab01 for example (The file name can be different from the project
name) and select Verilog as Add file as type option.

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 You will see lab01.v file added to your workspace as shown below:

3. To start typing in your code, Double Click the file name to edit it. The Editor window
appears and you can start your coding in this window.

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Type in the example code for AND gate given to you and save it.

4. The next step is to compile the code. In the toolbar, select the compile icon (first
icon) to compile it.

A dialog box asking Add to Project appears. Click Yes to add the file (lab01.v) to your project.

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If you have made No mistake in coding, then you can see a message telling you about the
successful compilation of lab01.v.

5. The next step is to simulate this code.

Go to Simulate>Simulate

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A Simulate window appears

Expand the work option and select the name of your test bench module like stim in this case.

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Click OK and you can see the stim module added to your workspace.

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 6. Viewing Waveform: Right Click stim. Select Add>Add to Wave.

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You will see the wave window appear

To view simulation results select the Run All option from the toolbar in wave window.

Select zoom in option to zoom into waveform.

Right Click the /stim/Out and Select Radix>Binary.

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The final waveform appears as follows:

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Part (b): Getting Started with Verilog HDL
Introduction:

With the ever increasing complexity of modern circuits and digital systems, it is very difficult
(almost impossible) to design the system directly on hardware (by picking up the physical up
components and placing them right away). If somehow we are able to do that, then the
verification or testing of the system takes a lot of time and we have No before-hand method to
verify the functionality of our system unless we have physical systems in our hands.

In order to overcome this problem and several other issues, the computer languages for
designing and simulating circuits have been introduced so that we can verify the functionality of
our system and modify if needed before actually producing a physical hardware system. As
opposed to our conventional computer programming languages (in which we are programming
the Computer, the existing hardware), the languages used to design circuits are essentially
defining and describing the new hardware we want to produce so these languages are termed
as Hardware Description Languages and fall in category of low-level programming languages.
Although most of the HDLs are used for digital circuits, yet there are some modifications which
allow analog components to be included is design as well.

The two major versions of HDL are VHDL and Verilog HDL. We would be using the Verilog
HDL or Verilog in this course. The software we would be using for compiling and simulating
Verilog is ModelSim SE 5.7f. To get familiar with the ModelSim you may refer to tutorial
Getting Started with ModelSim. This tutorial covers the introduction to Verilog and gate level
programming (to be explained later).

Verilog Modeling Levels:

In Verilog we have different abstraction levels as follows

Gate Level Modeling (using the basic gates and, or, Not, etc to and their inter-connection to
describe the whole system)

Dataflow Modeling (defining the flow of data among different components of design using
operators, No interconnection between gates needed)

Behavioral Modeling (defining the overall behavior of system like if input is x then output is y)

The abstraction level increases as we move from Gate to Behavioral Modeling.

There is yet aNother abstraction level Switch Level Modeling in which the transistor level of
hardware is dealt with. It is a very complex level and is only used in critical applications or part
of a system. In this course we will be dealing with the first 3 only.

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Verilog Module:

Verilog is a modular language which means the basic component of a Verilog code is a module
or in other words our Verilog code consists of one or more modules and these modules call
each other to perform the desired functionality. Let us start with writing a simple Verilog code
for designing and simulating a two input OR gate. We will be using ModelSim for compiling and
simulating our Verilog Code.

Before beginning the following section make sure that you have read the manual Getting
Started with ModelSim 5.7f.

Gate level Modeling

Module task1(out,in1,in2); , task1

moduleis the
is aname of module
keyword.
task1 is the name of our module.
Input in1,in2; out,in1,in2 are called ports of the module, they are likes parameters in C
language.
output out;
we define some of these ports as input or outputs. Here input and output
or a1(out,in1,in2); are keywords. You can define them in any order.
or is a keyword, it is one of the “primitives” or already define modules in
endmodule Verilog that implements the or gate.
We have called/invoked the already defined or gate and given the inputs
and outputs. a1 is the optional name we have given to gate invoked or
called by us. In Verilog terms it is known as calling an instant of the module
and a1 is name of the instant.
In primitive gates, always output ports are mentioned first and then input
ports.
endmodule is a keyword which defines the end of module .
The above code should generate an OR gate as shown.
Try to relate the actual OR gate shown and the Verilog code.

task1

in1 out

in2

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We have successfully implemented OR gate in Verilog. The next step is to check its functionality
by giving it some inputs as you have done in actual hardware by giving logic 1 (+5V) and logic 0
(0V). In Verilog we write another module for this purpose which is called a testbench or
stimulus. Testbench or stimulus is also a module.

module test1; module is a keyword.

test1 is the name of our module. Notice it has No ports.
reg IN1,IN2;
You Notice two new key words reg and wire. These are two of the data
wire OUT; types in Verilog. reg data type is used whenever you want to store a value
and wire can be thought of the simple wire as in hardware. The details of
task1 t1(OUT,IN1,IN2); them will come in further labs. For the time being, just make sure that you
define the inputs in your design module (task1 in this case) as reg and
initial
outputs as wire in testbench.
begin
task1t1(OUT,IN1,IN2); Here we are calling our above moduletask1 and
#100 IN1=1'b0;IN2=1'b0; giving it a instant name t1 like we called or gate and gave it name a1.
initial and begin are two other keywords and their details will we
#100 IN1=1'b0;IN2=1'b1; explained later. Anything after initial will be executed sequentially once.

#100 IN1=1'b1;IN2=1'b0; #100 denotes a delay of 100ns or whatever your timescale is defined. By
default, in most of the simulators it is in ns.
#100 IN1=1'b1;IN2=1'b1;
We are giving the values to inputs IN1 and IN2 in a logical manner as we
end
did in hardware or while making truth table. You may give them in any
endmodule order.

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Results of Simulation in ModelSim

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