MODULE –I Basic 80x86 Architecture Role of Microprocessor in Micro Computer – Brief history of

Microprocessors (with specific insight into x86 family) - Features of 8086 Internal Block Diagram of 8086 –
Execution Unit – Bus Interface Unit – Addressing Modes Hardware structure of 8086- Pin Configuration-Clock-
Processor activities (Interrupt, DMA, etc.)- Maximum mode- Instruction cycle Assembly process – Assemblers
for x86 – Instruction Design

Microprocessor
• The microprocessor, also known as the Central Processing Unit (CPU), is the brain of all
computers and many household and electronic devices.
• It is actually a silicon chip that contains a CPU.
• In the world of personal computers, the terms microprocessor and CPU are used
interchangeably.

or
• The microprocessor is a multipurpose,  programmable device that accepts digital data as input,
processes it according to instructions stored in its memory, and provides results as output
Role of Microprocessor in Micro Computer
• A microcomputer system is one which uses a microprocessor as its cpu
• In addition, the microcomputer also has a memory unit, input/output devices and system
buses.
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Features of 8086
 16bit processor.
- It’s ALU, internal registers works with 16bit binary word
 16bit data bus.
- It can read or write data to a memory/port either 16bits or 8 bit at a time
 20bit address bus
- it can address upto 220 = 1MB memory location; 0 to 1048575 or 00000 – fffff H
 Frequency range: 6-10 MHz
 It consists of powerful instruction set, which provides operations like multiplication and
division easily.
 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance.
 It has an instruction queue, which is capable of storing six instruction bytes from
the memory resulting in faster processing.

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  It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode
is suitable for system having multiple processors and Minimum mode is suitable for system
having a single processor.

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Internal Block Diagram of 8086
Architecture of 8086

 8086 is 16 bit microprocessor ie. Data bus and internal registers are of 16 bit in width
 It has 20 bit address bus ( A0 to A19 ).Can address up to 220 = 1 megabytes of memory space.
 Also has the capacity to work on 8 bit data.

 The internal block diagram has been partitioned into two logical units - Bus Interface Unit
(BIU) and Execution Unit (EU)
 BIU and EU interact through the internal bus.
Execution Unit
• EU is responsible for executing the instructions of the programs and to carry out the
required processing

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Functions of EU
 To tell BIU, from where to fetch the instructions or data.
 To decode the instructions: A decoder in the EU control system translates instructions.
 To execute the instructions.
 Contains ALU, Control unit, Internal bus ,Registers.

1. Arithmetic Logic Unit ( ALU )

 Part of computer which performs all arithmetic and logic computations.
 Most important unit of processor.
 Instructions fetched and decoded are executed by ALU
 It has direct access to general purpose registers and flags.
2. Registers

The EU contains the following 16-bit registers

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
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SP - the Stack Pointer \ defaults to stack segment

BP - the Base Pointer /

SI - the Source Index Register
DI - the Destination Register
Flag Register
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General Purpose Registers.
 There are four general purpose 16 bit registers AX,BX,CX and DX. These are also
called the Data Registers.
 The data/general purpose registers can be used for
 holding data and variables
 storing intermediate result temporarily.

 These registers can be used as 8-bit registers AH, AL, BH, BL, CH, CL, DH, and DL.
 These can be used as 16-bit in pair to have AX, BX, CX, and DX to store 16-bit data.
 AX Register: AX register is also known as accumulator register that stores
operands for arithmetic operations .
 BX Register: This register is mainly used as a base register. It holds the starting
base location of a memory region within a data segment.
 CX Register: It is defined as a counter. It is primarily used in loop instruction to
store loop counter.
 DX Register: DX register is used to contain I/O port address for I/O instruction.

• Data Registers are general purpose but they also perform special functions
AX-Accumulator register . It is used for all
– Input/output operations
– arithmetic operations
– string manipulation
BX-Base register- used as offset storage for generating physical addresses in case of
certain addressing modes.
CX- Count register
– Used as a loop counter
– Used in shift and rotate operations

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 DX-Data register
– Used in multiplication and division
– Also used as a port number in I/O operations

Pointer and Index registers

 Pointer registers (SP, BP, IP): Contain the offset or logical address of memory
locations
• IP (Instruction Pointer) holds the 16-bit offset address of the next code byte
within code segment.(hold offset of CS register).
• BP (Base Pointer) holds offset for DS Register
• SP (Stack Pointer) holds offset for SS Register. used to access data in the
stack segment
 Index registers (SI, DI)
• used as a general purpose registers as well as for offset storage
• used to access data stored in arrays
• required for some string operations.
• In string movement instructions SI point to the source string and DI points to the
destination string.

Flag Register
 Flag Registers of 8086 is also called status register. It keeps the current status
of the processor

 Flag register in EU is of 16-bit and is shown as below

8086 has 9 flags and they are divided into two categories:
1. Conditional Flags -represent result of last arithmetic or logical instruction executed.

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 2. Control Flags Used to control some operations of the MPU.
These flags are to be set in order to achieve some specific purposes.

Conditional flags are as follows

• Carry Flag (CF): This flag is set when an arithmetic carry or borrow has been generated out
of MSB after an arithmetic addition/ subtraction operation.
• SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
• ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes)
• AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized arithmetic.
• PF (parity) Indicates the number of 1 bits that result from an operation.
• OF (Overflow Flag) Indicates overflow of the leftmost bit during arithmetic.
Control flags are as follows
• DF (Direction Flag) Indicates left or right for moving or comparing string data.
• IF (Interrupt Flag) Indicates whether external interrupts are being processed or ignored.
• TF (Trap Flag) Permits operation of the processor in single step mode.

Bus Interface Unit (BIU)

• The BIU fetches instructions, reads and writes data, and computes the 20-bit address.
The function of BIU
 Fetch the instruction or data from memory.
 Write the data to memory.
 Write the data to the port.
 Read data from the port.
BIU Contains Instruction Queue, Segment Registers, Bus control Logic etc
Instruction Queue
6-bytes of instruction are fetched in advance and kept in a 6-byte Instruction Queue to
support pipelining. First-In-First-Out (FIFO).
The BIU contains the following segment registers:
CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register
• Memory is divided into four segments namely Data ,Code, Stack and Extra segments .
• This segmentation is done to keep data and code separately.
• Segment registers (DS,CS,ES,SS registers)stores the base address (16 bit)of each Segment.
• The starting address of segment is called base address or segment address.

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Functions of Segment Registers
• CS register holds 16-bits starting address of code segment
• SS register hold the starting address for the current stack.
• DS Register: Points to the current data segment.
• ES registers are used to hold the starting address of the extra segment.

Memory Segmentation
 8086 has 20bit address bus and so the available memory space is 220 = 1MB
 Addresses are expressed as 5 hex digits from 00000 – FFFFF H
 But 20 bit addresses are TOO BIG to fit in 16 bit registers!
 So this memory is divided into 4 logical segments.
 That is within the 1 MB of memory, the 8086 defines 4 64KB memory blocks or segments.
 Means each segment is 64Kbytes in size and addressed by one of the segment registers.
 In 8086 microprocessor, memory is divided into 4 segments as shown here

Segment Resisters and memory segmentation

• These segment registers are used to hold the 16bit starting address for each of the segments.  
• Segment Starting address is also called base address.

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 • Within a segment, a particular memory location is specified with an offset.
• A logical address is a combination of a segment address and an offset
• It is specified as segment:offset
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Addressing Modes
 An instruction is divided into Opcode and Operand. Opcode specifies what an instruction does ,
operand specifies the data .

 Addressing mode is defined as the method of specifying an operand.

 Operands may be in REG, Memory, I/O ports, and within Instruction itself.
 The 24 types of addressing modes in the 8086 can be grouped into the following categories.
1. Immediate Addressing Mode
2. Implicit Addressing Mode
3. Register Addressing Mode
4. Direct Addressing Mode
5. Register Indirect
6. Based Indexed
7. Register Relative
8. Relative Based Indexed
Note:
 The 8086 processor instruction MOV can be used to explain the addressing modes.
 The format of move instruction is
MOV destination, source
It moves the contents of source to destination.

1. Immediate Addressing mode

• Here data is a part of the instruction.
• The data on which instruction operates is combined with the instruction itself.
Eg.
MOV AX, 100
• Here data 100 is a part of the instruction and this instruction copies the value 100 into register
AX.
2. Implicit Addressing Mode
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• Here the instruction does not have any operand
• Here the instruction assumes data within a pre-defined register.
• The register on which implicit addressing instruction operates vary from instruction to
instruction.
Eg : CMC –complement carry flag
STD - set direction flag
CLC - clear carry flag
Here the data is in the flag register.

3. Register addressing

 Here both source and destination operands are registers

Eg: MOV AX, BX
ADD BX, AX
SUB BP, CX
The above instructions use only registersImmediate addressing
4. Direct addressing
 Here, the effective address of the memory location at which the data operand is
stored is given in the instruction.
 The effective address is just a 16-bit number written directly in the instruction.
Eg: MOV BX, [1354H]
MOV BL, [0400H] 
This instruction moves data from location 0400H in the data segment into BL.

 The square brackets around the 1354H denotes the contents of the memory
location. When executed, this instruction will copy the contents of the memory
location into BX register.
 This addressing mode is called direct because the displacement of the operand from
the segment base (offset)is specified directly in the instruction.

5. Register Indirect addressing

• Address of the memory location which contains data/operand is determined in an
indirect way.
• Instruction specifies a register which contains an address (offset)where data is located
• The offset address of the data is in one of the following registers:- [BX], [SI] or
[DI]
eg. MOV AX, [BX]

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• Suppose BX:0030H . This instruction causes data from offset 0030h in Data segment to move
to AX.
ADD AX,[SI]
SUB AX,[DI]
6. Based Indexed Addressing mode
• The content of base register [BX] or [BP] is added to the content of an index register [SI] or
[DI].
• The resulting value points to the location where the data is present.

eg. MOV AX,[BX][SI]

Data resides at an offset address [BX]+[SI] in Data Segment

7. Register Relative Addressing mode

 8 bit or 16 bit displacement is added with contents of any one of [BX], [BP], [SI] or
[DI]

Eg. Mov AX,50H[BX]

Data resides at an offset address [BX]+ 50H in Data Segment

8. Relative Based Indexed Addressing mode

 8 bit or 16 bit displacement is added with contents of base register ([BX] or [BP])
and index register ([SI] or [DI] )
 The resulting value points to the location where the data is present.

 Eg. Mov AX, 50H[BX][SI]

 Data resides at an offset address [BX]+ [SI]+ 50H in Data Segment

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 Hardware Structure of 8086

AD0-AD15 (Bidirectional)
 Address/Data bus
 Low order address bus; these are multiplexed with data.
 When AD lines are used to transmit memory address the symbol A is used instead of AD, for
example A0-A15.
 When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-
D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
 High order address bus. These are multiplexed with status signals
BHE (Active Low)/S7 (Output)
 Bus High Enable/Status
 It is available at pin 34 and used to indicate the transfer of data using data bus D8-D15.
 It is used to indicate the transfer of data over the higher order data bus (D8 to D15).

 This signal is low during the first clock cycle, thereafter it is active
RD (Read) (Active Low)
 The signal is used for read operation.
 It is an output signal.
 It is active when low.
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ALE
 This signal indicates the availability of a valid address on the address/data lines.

TEST

 input is tested by the ‘WAIT’ instruction.

 8086 will enter a wait state after execution of the WAIT instruction and will resume execution
only when the is made low by an active hardware.

 This is used to synchronize an external activity to the processor internal operation.

READY
 It is available at pin 32.
 It is an acknowledgement signal from I/O devices that data is transferred.
 It is an active high signal.
 When it is high, it indicates that the device is ready to transfer data. When it is low, it indicates
wait state.
RESET (Input)
 It is available at pin 21 and is used to restart the execution.
 It causes the processor to immediately terminate its present activity.

 This signal is active high for the first 4 clock cycles to RESET the microprocessor.
CLK
 The clock input provides the basic timing for processor operation and bus control activity.
INTR Interrupt Request
 This is a triggered input.
 This is sampled during the last clock cycles of each instruction to determine the
availability of the request.
 If any interrupt request is pending, the processor enters the interrupt acknowledge cycle.
 This signal is active high and internally synchronized.

MN/MX
 The 8086 microprocessor can work in two modes of operations : Minimum mode and
Maximum mode.
 In the minimum mode of operation the microprocessor do not associate with any co-
processors and can not be used for multiprocessor systems.
 In the maximum mode the 8086 can work in multi-processor or co-processor
configuration.
 Minimum or maximum mode operations are decided by the pin MN/ MX(Active low).
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 When this pin is high 8086 operates in minimum mode otherwise it operates in Maximum
mode.

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 , (Queue Status) The processor provides the status of queue in these lines.
The queue status can be used by external device to track the internal status of the queue in
,  (Bus Request/ Bus Grant) These requests are used by other local bus
, , Status signals; used by the
masters to8086
forcebus
the controller
processor to generate
release thebus
local bus at the end of
timing and controlthesignals. Thesecurrent
processor’s are decoded as shown.
bus cycle.
 These pins are bidirectional.
 The request on will have higher priority than

8086.
The output on QS0 and QS1 can be interpreted as shown in the table.

LOCK
 Output signal from 8086.
 If this signal is low, processor prevents any other bus masters from accessing the
bus.

Instruction cycle
 The time taken by the processor to execute an instruction.
 Specified in terms of number of clock cycles.
 Instruction can be decomposed into
o Fetch Instruction (FI)
o Decode instruction (DI)
o Calculate Operand Address(CO)
o Fetch Operands ( FO)
o Execute Instruction (EI)
o Write or store result in memory (WO)
 The time for all these activities constitute the instruction cycle.

Minimum and Maximum Modes of 8086

• The minimum mode is selected by applying logic 1 to the MN / MX’ input pin.
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• This is a single microprocessor configuration.
• In this mode, all the control signals are given out by the microprocessor chip itself.
• The maximum mode is selected by applying logic 0 to the MN / MX’ input pin.
• This is a multi micro processors configuration-means in the maximum mode, there may be
more than one microprocessor in the system configuration.
• In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
Assembler
• Systems Level Program that translates assembly language source code to machine language
• That is assembler converts computer instructions into a pattern of bits that the computer's
processor can use to perform its basic operations.
• The conversion process is referred to as assembly, or assembling the code.
• Assembly Language Programming:Using symbolic instructions to represent the raw data that
will form the machine language program and initial data constants

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