1 International Journal for Research in Engineering Application & Management (IJREAM)

ISSN : 2494-9150 Vol-01, Issue 12, MAR 2016.

Study of Multicore processors: Advantages and

Challenges
1Vinayak Shinde, 2Anas Dange, 3Muhib Lambay
1
Assistant Professor & H. O. D., M. E. Scholar, 1,2Shree L. R. Tiwari College of Engineering, Mira Road, India,
2
3
Assistant Professor, Theem College of Engineering, Boisar, India,
1
[email protected], [email protected], [email protected]

Abstract Multi-core processors have reformed the digital world today which is inhabited by us and still the endless efforts
are being carried out to generate faster and smarter chips. Since the most significant direction to expand the performance
of processor is Multi-core, the manufacturers are highly focused on this technology. Multi-core processors allow higher
performance at lower energy which can boost the performance of mobile devices that operate on batteries. Also, the
consorting capability of these multiple cores upturns the multitasking ability of the system. That is the cores work
together by executing multiple instructions simultaneously using parallelism in an efficient manner. In addition to this,
the adjacency of multiple CPU cores on the same die grants the cache coherency to operate at a much higher speed than
what would have happen if the signals had to travel off-chip. This in turn leads to the less degradation of signals since
they had to travel shorter distances between different CPUs. All these factors have led to the evolution of many new
multi-core processors like R65C00 and many others by Intel, AMD, etc. But, the improvement in performance achieved
by the multi-core processor is very much depended and limited by the fraction of the software and its implementation
which can run simultaneously on multiple cores whose effect is described by Amdahl's law. In spite of these indispensible
benefits, there are certain biting challenges that need to be taken care of before going in for this technology. This paper
introduces the technology of multi-core processors and its advantages in today’s world. Finally, the paper concludes by
detailing the challenges that are presently faced by multi-core processors.

Keywords — Amdahl’s law, cache coherence, mobile devices, multi-core, parallelism, smart chips.

smarter chips. Some of the techniques that have been

I. INTRODUCTION1 advised to improve the performance include pipelining and
different levels of parallel processing like data level and
Until few years back, we have been working with the instruction level parallelism which has proved to be very
processors having a single central processing units that read effective. One such technique that manufacturers came up
and execute program instructions called a core. The first with; which improves the performance significantly is a new
microprocessor had only 2200 transistors [1].The design of processors called as multi-core processors. This
performance of these single core processors cannot be concept of multi-core processors started evolving when
boosted beyond the certain limit as the power dissipation Gordon Moore, the co-founder of Intel and Fairchild
increases with the escalation of the clock frequency. Semiconductor, in April 1965, wrote an article for
Parallelism is one of the finest ways to solve the issue of Electronics magazine titled "Cramming more components
power along with the maintenance of performance which onto integrated circuits" [2] which later came to be called as
can be achieved with lower frequency and voltage. This will Moore's law. Obviously it should be considered as an
result in the bigger transistor count, but overall less power observation or projection and not a physical or natural law.
dissipation and power density. This idea led to the It is the consideration that the number of transistors in a
foundation of multi-core. dense integrated circuit doubles approximately every two
years and projected this rate of growth would continue for at
The flourishing market and the demand for increasing least another decade. In 1975, looking forward to the next
performance led the industries to manufacture quicker and decade, he revised the forecast to doubling every two years
[3]. Thus A multi-core processor provides lot of advantages
especially for those looking to expand their system’s
multitasking computing power. In this article, our main goal

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 International Journal for Research in Engineering Application & Management (IJREAM)
ISSN : 2494-9150 Vol-01, Issue 12, MAR 2016.

is to describe some of the significant challenges of multi- work on programs. If one of the processes fails to complete
core processors. In addition, the paper also discusses the on time then all the rest of the processes start lagging
advantages along with its basic concept. behind. However, In the case of multi-core processors if
multiple tasks run in parallel at the same time, each of them
II. MULTICORE PROCESSORS will be executed by a separate core simultaneously thus
Multi-core processors have been in reality since the past promoting the performance [4]. Additionally, multi-core
decagon, but however it have earned more significance off processors are generally designed in such a way that can run
late due to some of the technological limitations like large more efficiently than a single processor, since not all the
throughput and long-term battery life with tremendous cores need to be active unless needed. For example, the
energy efficiency. power is turned off to entire cores for Intel's "Turbo Boost
Technology" when they are not being used. One important
A multi-core processor comprises of a single computing point to understand is that multiple cores are different than
component with two or more independent actual multiple CPUs.
computational or processing units, called as "cores", that
which are the units that operate in parallel to read and There are number of topologies that are being practiced to
execute programming instructions. These are simple CPU interconnect multiple cores like Ring topology, Bus
instructions like arithmetic operations, move data, and topology and Two-dimensional topologies such as mesh and
branch instructions, but the prime thing is that multiple crossbar. The performance parameters like speed; latency
cores can execute multiple instructions at the same time, etc. is affected by the choice of particular topology. Hence
thus increasing the overall speed for programs similar to its selection is an important factor as the type of topology
parallel computing. Manufacturers typically fabricate the also impacts area consumed on a chip and power
cores onto a single integrated circuit die or onto multiple dissipation.
dies in a single chip package. Hence it’s also called as a
Chip Multiprocessor (CMP). The prime factor about
multicore processor is that the performance of these
processors is not degraded as compared to a single
processor even with lesser power dissipation and at a lower
clock frequency. The performance of any processor mainly
depends on following three major factors:

1. Instructions per cycle (IPC), which can be improved by

increasing Instruction Level Parallelism and Thread Level
Parallelism.

2. Clock cycles per instruction (CPI) which can be Figure 1: Multicore processors
improved by the techniques of pipelining and
In addition to this, there are two types of cores used by
3. Clock frequency. multicore technology namely homogeneous and
heterogeneous cores. As the name suggest, in homogeneous
But if we increase the clock frequency beyond certain limit, configuration, all the cores are indistinguishable and each
the power dissipation increases which in turn causes since P core has same hardware where as there are dedicated
is directly proportional to f. So, the idea of multicore applications specific cores which work on specialized
technology is to use more than one core instead of one at a applications in heterogeneous cores. Sometimes Multicore
comparatively lower frequency. These cores execute Processors combine the positives of both homogeneous and
multiple threads that is, multiple instructions while heterogeneous configurations to improve their performance.
accessing multiple data from different parts of memory. The IBM multicore processor, CELL uses this approach.
Each core is having its own cache while the system bus and The wide range of applications for multi-core processors
main memory is shared by all cores. includes domains like general-purpose, embedded systems,
digital signal and image processing, and networking. Also,
The single core processors where multiple programs are the industrial applications of MCPs incorporate motion
running simultaneously would assign different time slice to control, machine vision, automated test systems and CAD

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3 International Journal for Research in Engineering Application & Management (IJREAM)
ISSN : 2494-9150 Vol-01, Issue 12, MAR 2016.

systems. programming for multi-core architecture is more

complicated than conventional parallel programming. These
Processors were originally developed with a single core. challenges must be dealt with a holistic approach to support
However, in the mid-1980s, Rockwell International emerging programming models for multi-core processors
manufactured versions as the R65C00, R65C21, and and devise efficient methods of multi-core programming.
R65C29 with two cores on one chip sharing the chip's pins
A. Memory Hierarchy
on alternate clock phases. In 1996, a hand-picked team of
some 250 system and chip designers, software architects,
researchers and semiconductor engineers successfully put One of the most demanding challenges that are faced by
two high-performance microprocessor cores on a single multi-core processors today is its memory system. The
silicon chip called as IBM’s POWER4 which combined the execution of a program is often bounded by the memory
best of commercial, scientific and high-performance bottleneck which happens not due to the non-availability of
computing in a single design [5]. Intel came up with its first processor and its low speed but because of the fact that a
dual core processor in 2005. Multi-core processors may heavy portion of applications always lies in main memory
have two cores that is, dual-core CPUs, for example, AMD until it is executed by the processor. Moreover, multi-core
Phenom II X2 and Intel Core Duo, three cores i.e., tri-core processors can even make the situation more badly. Thus,
CPUs, for example, AMD Phenom II X3, four cores that is, care should be taken to conserve memory bandwidth and
quad-core CPUs, for example, AMD Phenom II X4, Intel's avoid memory contention. Also, it is significant to note that
i5 and i7 processors, six cores i.e., hexa-core CPUs, for the memory hierarchies in parallel machines are more
example, AMD Phenom II X6 and Intel Core i7 Extreme difficult than in the uni-processor's machines, especially in
Edition 980X, eight cores called as octa-core CPUs, for multi-core processors where L2 and L3 cache are shared by
example, Intel Xeon E7-2820 and AMD FX-8350, ten cores the multiple cores with in a chip. This leads to more
i.e., deca-core CPUs, for example, Intel Xeon E7-2850, or complicated memory hierarchy design in CMPs.
more [3]. B. Cache Levels
The current trend of multi-core processors which are
general purpose use 3-level cache scheme consisting of L1,
III. ADVANTAGES OF MULTICORE PROCESSORS L2 and L3 cache. The present 3-level cache system is
working fine with the current dual, quad and eight cores
1. The Multi-core processors can deliver a very high
processors. In this cache model, the L2 cache may be
performance benefits for multi-threaded software by adding
private, shared or split. But as number of cores increases,
more and more processing power with minimal latency,
this may cause the bottleneck and result in data traffic
given the proximity of the processors.
congestions and performance degradation.
2. The most significant benefits will be viewed in many
applications such as Customer Relationship Management, C. Cache coherence
larger databases, Enterprise Resource Planning, ecommerce “Cache coherence is the discipline that ensures that changes
and virtualization. in the values of shared operands or data are propagated
3. The more threaded applications will clearly get more throughout the system in a timely fashion” [6].
benefit. In a due course of time, this trend is beginning to When caches of a common memory resource is maintained
and will shape the future of software development towards by the clients in a system, then complications may arise with
parallel processing. the inconsistent data, which is especially a concern in a
4. Meantime, we can target the quad-core servers for multi-core environment because of sharing of L1 and L2
those types of applications which can get the maximum cache. Let’s take an example of a dual-core processor where
work out of them. each core transfers a block of data from memory into its
private cache. First core writes a value to a specific memory
IV. CHALLENGES INVOLVED IN MULTI-CORE location; when the second core tries to read that value from
PROCESSORS its cache it will not have the updated copy unless a cache
The two main characteristics that uniquely identify Multi- miss occurs. This cache miss forces the update operation on
core architectures are heterogeneity and the massive the second cores cache entry. If this policy would not have
parallelism in addition to any arbitrary topology for been in place then invalid results would have been
interconnection of processors or cores. Thus, parallel produced. Since the shared and private caches exist at

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 International Journal for Research in Engineering Application & Management (IJREAM)
ISSN : 2494-9150 Vol-01, Issue 12, MAR 2016.

different levels in multi-core processors, this cache G. Power and temperature

coherence problem becomes worse. As the number of cores placed on a single chip increases
D. Developing Multicore Softwares without any modification, the chip will consume more
power leading to the generation of large amount of heat,
One of the significant issues seen with regard to software
which can even cause your computer to become combust; if
programs is that they run a bit slower on multi-core
the processor overheats. To reduce this unnecessary power
processors as compared to single core processors. It is being
consumption, the multicore designs also incorporate a
correctly pointed out that “Applications on multi-core
power control unit that can force the unused cores to shut
systems don’t get faster automatically as cores are
down that are not required at times. The core which
increased” [7]. So, the solution is that the programmers
overheats in a multicore configuration is called a hot-spot.
must develop programs and applications that can exploit use
The chip is architected such that the amount of heat
of the increasing number of processors in a multi-core
generated in the chip is well distributed across the chip. The
environment. Also, the time needed to write these softwares
majority of the heat in the CELL processor is dissipated in
cannot be stretched. Moreover, majority of applications
the Power Processing Element and the remaining is spread
used today are written to run on a single core processor,
out across the Synergistic Processing Elements. There are
which failed to use the capability of multi-core processors.
various ways to tackle the problem of power dissipation and
Hence, the dignified challenge the industry faces is how to
temperature which includes thread migration, DVFS
port these software programs which were developed years
(Dynamic Voltage and Frequency Scaling) etc. In the thread
ago to multi-core adaptable software programs. Although it
migration technique, a low power consuming process or
sounds very possible to redesign programs, it’s really not a
thread is moved to an overheated core. In DVFS (Dynamic
business profitable decision in today’s world where in
Voltage and Frequency Scaling) technique, voltage and
companies have to keep in mind the key parameters like
frequency of the hot core is reduced since the power
time to market, customer fulfillment and cost cut. It has
dissipation or heating is a function of both voltage and
however been correctly pointed out that “The throughput,
frequency which slightly affects the overall performance
energy efficiency and multitasking performance of multi-
also [9].
core processors will all be fully realized when application
code is multi-core ready” [8]. H. Communication Minimization or Interconnect Issues
E. Level of Parallelism Another important feature which impacts the program
execution and its performance in multi-core processors is
The level of parallelism of the process is one of the gigantic
the interaction between on chip components viz. cores,
factors that affect the performance of a multicore processor
cache, memories and if integrated—memory controllers and
significantly. Performance will increase with the decrease of
network controllers which are used for memory-memory
completion time of a process. Parallelism can be achieved
and memory-processor communication; where bus
by Instruction Level Parallelism and Thread Level
contention and latency are the key areas of concern. In
Parallelism. TLP increases overall parallelism by breaking a
multi-core processors, as the number of cores and respective
program into many small threads and execute them
caches increases, the inter-memory and memory-processor
concurrently. Hence to achieve a high level of parallelism,
communication is expected to increase exponentially. So,
software developers must write such algorithms that can
the memory hierarchy of multi-core processors should be
take full advantage of multicore design. Also, companies
designed in such a way that these communications are
like Microsoft and Apple have designed their operating
contained. It is rightly pointed that: “The performance of the
systems which can run efficiently on multicore
processor truly depends on how fast a CPU can fetch data
configuration [9].
rather than how fast it can operate on it to avoid data
F. False-Sharing starvation scenario” [10]. Special crossbars or mesh
If two different processors operate on independent data in technologies have been enforced on hardware to solve this
the same memory address region that reside on the same issue. For instance, AMD CPUs employ a crossbar, and the
cache line and the mechanism may force the whole line to Tilera TILE64 implements a fast non-blocking multi-link
interconnect with every data write, forcing the wastage of mesh [11].
system bandwidth is termed as False-sharing. In multi-core
processors, with the increase in number of cores, the
number of private and shared caches will also increase and
this might result in increase of false-sharing.

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5 International Journal for Research in Engineering Application & Management (IJREAM)
ISSN : 2494-9150 Vol-01, Issue 12, MAR 2016.

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