Basics of Floating Gate Memory

Floating gate memory uses a MOSFET made with two layers of poly silicon as
shown in Fig 1.1. Figure 1.1 also shows its schematic symbol and a typical
layout.
As seen in the figure, the poly1 is floating, that is, not electrically connected to
anything (neither to VDD nor to Ground). A dielectric (SiO2) surrounds this
floating island of poly1.

OR

Figure 1.1: A floating gate MOSFET, its symbol and layout

Poly2 is placed above poly1 (floating gate). A thin oxide insulates the poly1
from p-substrate of MOSFET.
Poly2 is the controlling gate of the transistor (the terminal we drive to turn the
MOSFET on).
This cell is used as a memory element by changing, adding or removing, the
charge stored on the floating gate.
Figure 1.2 shows the difference between the erased state and the programmed
state in a floating gate memory.
The erased state is the state of the memory when there are no charges stored
on floating gate. When memory cell is fabricated, it has erased state. In erased
state, MOSFET has normal behavior.

Figure 1.2: Programmed and erased states of a floating gate memory.

As studied earlier, above the threshold voltage, the MOSFET device turns on
and conducts a current.
When the cell is programmed, we force a negative charge (electrons) onto the
floating gate (how we force this charge i.e programming will be discussed
shortly).
This negative charge attracts a positive charge beneath the gate oxide (Fig
1.3).
The result is that a larger controlling gate voltage must be applied to invert the
channel and turn the device on. Thus, in programmed state the threshold
voltage of MOSFET increases as seen from figure 1.2.
Programmed floating gate can retain negative charges for 10-20 years.
Figure 1.3: Trapped negative charge on the floating gate (Programmed state).

Types of floating gate memories are

1. EPROM
2. EEPROM (E2PROM)
3. Flash Memory
EPROM - Erasable Programmable Read-Only Memory
Erasable programmable ROM (EPROM) was the first floating gate memory that
could be programmed electrically.
To erase EPROM cell trapped charge on the floating gate has to be remove.
This returns the cell to its fabricated state. To erase, the cell is exposed to ultra-
violet light through a quartz(glass) window in the top of the chip's package (Fig
1.4).

Figure 1.4: EPROM ICs with glass window for UV light exposer.
The ultra-violet light increases the conductivity of the silicon-dioxide
surrounding the floating gate and allows the trapped charge to leak off.
This type of EPROM cannot be electrically erased. Hence, these have been
has replaced by Flash memory (discussed later) which can be erased
electrically.

Programming of EPROM cell

Programming the EPROM relies on Channel Hot-Electron (CHE) injection or
Hot carrier injection (HCI) phenomenon.
CHE is accomplished by driving the gate and the drain of the MOSFET to high
voltages (typically VDDP = 25 V) (Fig 2.1).
 Figure 2.1: Channel hot-electron (CHE) injection
The high voltage on the drain of the device causes hot electrons (those with
significant kinetic energy) to flow in the channel.
A large positive potential applied to the gate (poly2) attracts some of these
electrons to the floating gate (poly1).
The electrons can penetrate the potential barrier of SiO2 between the floating
gate and channel because of their large energies.

Self-limi ng programming
When we are programming the floating gate device, the accumulation of
electrons on the floating gate causes an increase in the device's threshold
voltage (Fig 1.2). The more electrons that are trapped the higher the threshold
voltage.
This increase in threshold voltage causes the drain current to decrease. The
decrease in drain current then reduces the rate at which the electrons are trapped
on the floating gate oxide.
If we apply the programming voltages for a long period of time, the drain
current drops to zero (or practically a small value). Because of this feedback
mechanism, the programming is said to be self-limiting.
We simply apply the high voltages for a long enough time to ensure that the
selected devices are programmed.

Programming Row of EPROM cells

Next examine Row of floating gate devices.

Figure 2.2: Programming Row of EPROM cells

When we are programming a row of cells, we drive the word line to a high
voltage. If the cell is to remain erased, we simply leave the corresponding bit
line at ground.
If the cell is to be programmed, we drive the bit line to the high voltage.
For CHE, both the drain and gate terminals of the floating device must be at a
high voltage.
EEPROM – Electrically Erasable Programmable Read-
Only Memory
EEPROM (E2PROM) is another type of floating gate memory.
Floating gate memory that can be both electrically erased and programmed is
called electrically erasable programmable ROM (EEPROM). Note that this
name is an oxymoron. If we can electrically write to the memory, then it isn’t a
read-only memory.
Individual memory cells in EEPROM can be programmed using CHE or FNT
mechanism. (FNT is explained later)
However, EEPROM is fabricate such that it can be erased electrically using
FNT mechanism instead of requirement of UV exposer as need in EPROM.
Flash Memory
Flash memory is another type of floating gate memory. It is designed to use
Fowler-Nordheim tunneling (FNT) [2] to program and erase memory cells.
Fowler-Nordheim tunneling (FNT) can be used to program or erase the
memory cells.
While CHE and FNT can be used together (CHE for the programming and FNT
for erasing) to implement a memory technology, we assume FNT is used for
both programming and erasing in the remaining discussion.
In flash memory a large amounts of memory cells (or a memory array
or memory rows) are erased simultaneously; hence it is called Flash
memory.
On other hand, to erase EPROM chip it has to be removed from the system and
exposed to ultra-violet for relatively longer time period. Also, EEPROM
memory cells can be programmed or erased individually.
Thus, General EPROM (EEPROM) arrays allow bit erasure i.e. each bit can
be erased individually. On other hand, flash EPROMs are wired in a manner
such that large blocks of cells can be erased simultaneously.
Flash memory (or flash EPROM) is particularly useful for temporary storage of
large data files such as those generated by digital photography. These are used in
flash drives (Pen Drives), SD cards, Solid State Devices (SSDs) etc.

Fowler-Nordheim tunneling (FN tunneling)

As discussed earlier floating gate memory cells of EPROM and EEPROM are
programmed using Channel Hot Electrons (CHE) injection method. Fowler-
Nordheim Tunneling (FNT or FN tunneling) is another mechanism to program
floating-gate memory cells.
To enhance Fowler-Nordheim tunneling the thickness of the oxide between
floating gate and channel is reduced from, say, 300 Ä (a typical value used in an
EPROM) to 100 Ä.
(Note: 1 angstrom unit = 1 = 10-10 meter = 0.1 nanometers = 100 picometers)
In this, gate geometry of transistor is modified so that a portion of the floating
gate extends over the n+ drain as shown in Figure 3.1. This design enables use
of Fowler-Nordheim emission as discussed below.

Figure 3.1 Fowler-Nordheim tunnelling

Figure 3.2 shows the basic idea of using Fowler-Nordheim tunneling (FNT) to
program a device. Programming means to trap electrons on the floating gate so
that the devices threshold voltage increases.
A large gate voltage is applied to create a large electric field between the
substrate and gate, which enhances the tunnelling of electrons through the
oxide.
Both the drain and source are grounded during the programming operation.
FN tunneling of electrons from the substrate (p-well) to a floating-gate increases
threshold voltage.

Figure 3.2: Programming using Fowler-Nordheim tunneling (FNT)

The control gate (poly2) is driven to a large positive voltage. For a 100 gate
oxide this voltage is somewhere between 15 and 20 V.
Note that we are assuming that NMOS devices are sitting in a p-well and p-well
is sitting in an n-well (so we can adjust the p-well [body of the NMOS]
potential).
The electrons tunnel through the thin oxide via FNT and accumulate on the
floating gate. Like programming in an EPROM device, this mechanism is self-
limiting. As electrons accumulate on the floating gate threshold voltage (Vth)
increases. This increasing Vth reduces the amount of tunneling current
gradually to zero (practically very small). This is self-limiting mechanism.
Note that if we didn't want to program the device when poly2 is at 20 V we
could hold the drain at a higher voltage (not ground) to reduce the potential
across the thin gate oxide (aka tunnel oxide).
The circuit of flash memory cell is shown in Figure 3.3.
Programming (or write) operation is accomplished by pulsing the Program
line i.e. pulling program line high. Word line is also pulled high as the same
time i.e. WL = 1. and the bit and source lines are both grounded.

Figure 3.3 Flash EEPROM cell with write line

Erasing Flash
Erasure is accomplished by reversing the polarity of the applied voltages.
To erase the device using FNT, examine Fig 3.4. Both the p-well and the n-well
are driven to 20 V while the control gate (poly2) is grounded.
 Figure 3.4: FNT of electrons from the floating gate to p-well to decrease
threshold voltage (showing erasing).

Electrons tunnel via FNT off of the floating gate (polyl) to the p-well.
The source and drain contacts to the device are floating. To accomplish this, we
will float the bit line and the source.
Again, the movement of charge is self-limiting (however, there are device issues
that can result in over erasing). The tunnel current drops as positive charge
accumulates on the floating gate.
If the erasing time is long, a significant amount of positive charge can
accumulate on the floating gate. This will decrease the threshold voltage of the
MOSFET.
Figure 3.5 shows the programmed and erase states for a Flash memory where a
positive threshold voltage indicates that the device is programmed and a
negative threshold voltage indicates that the device is erased (we show ± 3 V as
typical values).

Figure 3.5: Programmed and erased states of a flash memory.

Layout of 4-bit NAND Flash
The schematic and layout of a 4-bit NAND Flash memory cell is seen in Fig
3.6.

Figure 3.6: The schematic and layout of a 4-bit NAND Flash memory cell
The select transistors are made using single poly (normal) MOSFETs.
When the cell (all four bits) is erased, the p-well and the n-well are driven to
20V external to the memory array via the p+ implant.
The bit lines and the n+ source connection at the bottom of the layout are
floated.
The four control gates and the two select MOSFET gates are pulled to ground
(so all six poly gates, aka, word lines, are at ground for an erase).
To illustrate programming the floating gate MOSFET connected to RA0 (row
address 0), examine the connections to the NAND cell seen in Fig 3.7.

Figure 3.7: The bit programming in Flash memory.

A voltage, say 20 V, is applied to the gate of the top select gate RA0. The gates
of the floating gate MOSFETs connected to RA1-RA3 are driven to 5V.
This 5V signal turns on these devices but isn't so big that FNT will occur in
them. The bottom select MOSFET remains off so that there is no DC path from
the bit line to ground.
The p-well (which is common to all of the cells in the memory array, that is, not
just the four in the memory cell) is pulled to ground external to the memory
array via the p+ implant.
Because the gate, RA0, is pulled to 20 V and the drain implant is pulled to
ground through the bit line, the device will be programmed (electrons will
tunnel through the oxide and accumulate on the floating gate).
The next thing we need to look at before talking about reading the cell is how
we keep from programming the adjacent floating gate devices, those also
connected to RA0, if they are to remain erased.
What we need to do is ensure that no FNT occurs in these unselected devices.
Figure 3.8 shows how we keep from programming a device.

Figure 3.8: The bit line of the cell that is to remain erased is driven to a voltage
that is large enough to keep FNT from occurring.
The bottom select MOSFET is off, so there won't be a DC path from the bit line
to ground (this is important because all other MOSFETs in the memory cell will
be on).

Reading NAND Flash Cell:

To understand reading a NAND Flash cell, consider the Fig 3.9.
 Figure 3.9: Expanded view showing erased and programmed IV curves
To read Flash memory cell:
 both select transistors (Select-top and Select-bot) are turned on (say 5 V
on their gates).
 the unselected row lines (say RA1-RA3 are driven high (say, again, to 5
V), and
 the selected row line (here, RA0) is held at zero volts. (See fig 3.10)

Figure 3.10: Reading NAND Flash Cell

Then an average current, that is, (Ierased + Iprog)/2 is driven into the bit line.
If selected cell is erased then this MOSFET will sink a current of Ierased . This
will pull down bit-line low.
On other hand if the cell is in programmed state its MOSFET have larger
threshold voltage. Thus, it will not be able to sink current and bit line remains
high (actually it will sink only Iprog, which is very small [fig 3.9]).
Thus, the current difference between Ierased and Iprog can be used to determine if
the (selected) floating gate MOSFET is erased or programmed.
Conclusion is that, an erased cell will keep the bit-line at a low voltage and
programmed cell keep the bit-line high.
Table 1.1 shows a summary of erasing, programming, and reading a NAND
Flash memory cell.
References
• [1] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital
Integrated Circuits: A Design Perspective”, Pearson Education, 2nd Edition.
• [2] Lenzlinger, M., and E. H. Snow. "Fowler‐Nordheim tunneling into
thermally grown SiO2." Journal of Applied physics 40.1 (1969): 278-283.